Inside the AI Hardware Engine – Full Semiconductor Supply Chain Course

[00:00] Welcome to this conference of course on [00:01] the semiconductor supply chain where you [00:04] will learn how a chip moves from design [00:07] to the data center. You will learn all [00:09] about semiconductor physics, design, [00:12] fabrication, memory, packaging, and rack [00:16] scale integration. Your instructor Kon [00:19] will guide you through this journey to [00:21] help you understand the hardware [00:23] infrastructure powering modern [00:26] artificial intelligence. [00:28] >> All right. Hello everybody and welcome [00:29] to this video. My name is Kian and I'm [00:32] really excited for this course video [00:35] that I will be taking you through today [00:37] on the semiconductor supply chain called [00:40] chips where we'll be essentially [00:41] discussing how one AI accelerator moves [00:44] from design to data center through six [00:46] key phases. So we'll first talk about [00:48] like the physics of actually [00:50] semiconductors and transistors. Then the [00:53] design phase or EDA if you've heard of [00:55] that before we'll we'll discuss it. Then [00:57] the fabrication process, memory, [00:59] packaging, the logic and the memory [01:03] together into one device or one um [01:07] system and then at the end obviously [01:10] putting that into a rack scale data [01:12] center configuration. So in terms of [01:15] prerequisites for this course, there [01:18] isn't really much that you should have [01:20] to know. I'm assuming some exposure to [01:23] for example um different terms in like [01:27] GPU um memory etc like basic knowledge [01:30] of how computers work but apart from [01:33] that everything that is discussed in [01:35] this video is as close to first [01:37] principles as possible and when it comes [01:40] to why I'm making this tutorial like [01:42] what is the motivation itself first of [01:44] all right now you can see that um across [01:47] the world there is a massive investment [01:50] in hardware infrastructure and power etc [01:55] for serving AI models and many forecasts [02:00] demonstrate that this expenditure this [02:03] capex will only increase moving forward [02:05] and this means that this is no longer [02:06] like a niche topic that only few [02:10] understand or that only few should [02:12] understand which seems to have been the [02:14] case up to now right whereas now it's [02:16] becoming more and more mainstream and [02:17] this this course essentially serves to [02:20] elucid to date how this semiconductor [02:23] supply chain works, what are the diff [02:25] who are the different major players, [02:27] what are the bottlenecks etc. So that um [02:29] you can be informed on what different [02:32] processes are occurring and also if [02:34] you're interested in investing in [02:37] semiconductor stock which is a really [02:39] good way to essentially expose yourself [02:41] to the potential for growth in [02:44] particular with AI. Then this course [02:48] will also give you kind of the the [02:49] fundamentals of how to analyze value and [02:53] determine whether something is legit or [02:55] not when it comes to um the [02:57] semiconductor supply chain. And then [02:59] also there's this quote from Andre [03:00] Karpathy recently which I read that he [03:03] said you can export your thinking but [03:05] you can't export your understanding. And [03:07] this is in context of well now we can [03:10] essentially ask agents to think for us [03:12] and come back with some summary of a [03:16] research uh journey. But this does not [03:20] allow us to understand [03:22] uh and comprehend what is actually [03:24] happening behind the scenes which is [03:26] still extremely important. Like anybody [03:28] that says that you don't need to [03:29] understand things anymore you could just [03:30] ask a to do it is extremely misled in my [03:33] opinion. And um this course essentially [03:36] serves to help comprehend this this [03:39] industry which is as I've as I've [03:41] emphasized very important. One last [03:43] thing I want to mention before we get [03:45] started is the teaching format of the [03:47] course which is in the form of slides. [03:49] So I tried to make the slides as [03:51] pedagogical as possible and that is [03:54] essentially through having diagrams [03:55] which explain each concept in my opinion [03:58] an intuitive way and then also these [04:00] slides are actually on GitHub. Uh so the [04:02] course repository will be linked in the [04:04] video description and it's actually [04:06] hosted under GitHub pages at that same [04:08] repository. So you can also look on the [04:11] web page while you follow the course [04:13] where there's also the speaker notes if [04:14] you want to know more about a specific [04:16] slide than what I described. So without [04:19] further ado, we'll now go into the first [04:21] slide. So this course follows in [04:25] particular a single GPU um a Grace [04:30] Blackwell 300 Ultra from start to finish [04:34] of like how is this GPU created who are [04:37] the different key companies and [04:40] essentially parts in the supply chain [04:42] which allow this final product to be [04:44] made and um let's just present you what [04:47] this what this GPU is. So, the GB300 [04:49] compute board carries two Blackwell [04:52] Ultra GPUs, which you can see here on [04:53] the left and the right. One Grace CPU, [04:56] that's why it's called a GB, a Grace [04:58] Blackwell 300, and two Connect X8 Super [05:02] Nix, which are here. And once again, [05:05] we're going to follow this two compute [05:06] die um package through its entire um [05:10] supply and creation. So, I said toMP [05:13] compute die package. Um actually we're [05:15] going to discuss that in the next slide [05:17] of essentially how is this how is this [05:19] device made but um just to give you an [05:21] overview of how this uh how this how [05:23] this works essentially is [05:26] you have one of these boards which is [05:28] once again composed of two GPUs and if [05:30] you think of an NVL72 rack which is an [05:34] NVL link 72 rack of 72 Nvidia GPUs then [05:38] you'll have 36 of these stacked [05:40] vertically. Um, so because there's two [05:43] GPUs per board and this gives you a [05:45] single NVL 72 system. And then you may [05:47] have heard also of the DGX B300, which [05:50] is the other U B300 variant of the [05:54] Blackwell GPU. And just for curiosity, a [05:58] a DJX B300 is eight um B300 GPUs, so [06:04] these ones here, in a single rack system [06:07] without the CPU. So there's different [06:09] configurations of the u the GPU itself, [06:12] but we're going to talk about the GB300 [06:14] mainly in this course. And one thing [06:17] that I want to emphasize as well is the [06:18] connect x8 super nick. This is going to [06:21] allow me to explain the difference [06:22] between a scale up and a scale out [06:26] domain. So what do these do two terms [06:28] mean? Essentially when you have many [06:32] GPUs that host a single model since most [06:36] of the time your amount of memory is [06:38] insufficient for a single GPU to provide [06:41] inference for like a one trillion [06:42] parameter model. Um you need to you need [06:44] to essentially use model parallelism [06:46] which means splitting the model [06:48] splitting the activations etc across [06:49] multiple GPUs in order to serve that [06:51] model. And this is called the scale um [06:55] when this is within a single rack this [06:57] is called the scale up domain. And what [06:59] this means is you're serving the model [07:01] within a single uh contiguous rack which [07:06] has high bandwidth interconnect. So once [07:08] again the NV of the L7D2 system would be [07:11] the scale up domain across a single [07:12] rack. And then you have the scale out [07:15] domain which is essentially connecting [07:17] different heterogeneous systems um [07:20] across like for example data centers or [07:23] through lower bandwidth um interconnect. [07:26] And in fact, the reason why I'm saying [07:28] all this is because the connect x8 [07:30] supernix, which stands for network [07:32] interface card, this is the scale out [07:35] domain um connector. So essentially, if [07:38] you're bringing in whatever type of data [07:40] into this uh GPU from a different scale [07:43] up network. So perhaps like there's two [07:45] racks and they're connected via some [07:47] data center interconnect. Then the scale [07:49] out domain will connect it through this [07:51] connect 8 x8 supernick. And then you may [07:53] be wondering like within the rack [07:54] itself, how are you communicating [07:55] between GPUs? Well, this is through NV [07:57] link which is the uh bandwidth and [08:00] communication protocol for the scale up [08:03] domain. And the NV link is actually on [08:05] the GPU itself. So this is a great segue [08:07] to the next slide. And if you look here, [08:10] right, we have the NV link on the sides [08:13] of the GPU, which if we come here would [08:16] be right here on the top and bottom, [08:19] which you can call the shoreline. So the [08:20] shoreline in fact of the Blackwell Ultra [08:22] GPU is composed of the Envy link on two [08:25] sides and then the HBM the high [08:28] bandwidth memory on the other two sides. [08:31] There you can see um the complete uh GPU [08:34] with those two features. Okay. So I [08:38] talked about dyes in the previous slide [08:40] but I said let's not get ahead of oursel [08:42] and now we can discuss it in more [08:44] detail. So we have one GPU but two [08:46] reticlesized dies. So um let's talk [08:50] about what a die is but let's first um [08:52] determine where the two dies are. So [08:53] essentially you have this NVHBI in the [08:56] middle which separates the dyes from [08:59] each other. Um so what is a die? It's [09:01] essentially a wafer. So we have a [09:05] silicon wafer that is made in a [09:08] fabrication plant that is made through a [09:11] single reticle. And a reticle is you can [09:14] think of it as a lens which has the [09:16] pattern of the semiconductor. So a bunch [09:19] of transistors whatever those micrometer [09:21] nanometer patterns are that is then [09:25] essentially etched on the silicon in [09:27] order to create your accelerator chip. [09:31] And these have a certain size. So, we're [09:33] going to talk about the specific [09:35] dimensions in a bit, but what you need [09:36] to know is that the retical limit is [09:41] essentially not enough for what Nvidia [09:44] wants for the specific uh chip that [09:46] they're making, the GB300, which means [09:48] that they essentially had to make two [09:50] separate diese, which are essentially [09:52] the max reticle limit length, and then [09:54] attach them together. And in this way, [09:56] you have two dieseS, but one logical [09:59] GPU. And previously NV and GPUs were [10:02] only composed of one die. So it' be one [10:04] die, one GPU. But now it's actually two [10:06] dieseS but one logical GPU. And you may [10:08] be wondering how do you have two dieseS [10:10] which are in principle like [10:13] disconnected, right? Cuz you make one, [10:15] then you cut it out. Uh then you have [10:17] one die and then you make a second. [10:19] Well, it's through this um high [10:21] bandwidth interface that is die to die [10:23] which can transfer at 10 terabytes per [10:26] second. And this is called NVHBI, which [10:29] if you guess means Nvidia high bandwidth [10:31] interface. So pretty simple naming [10:34] convention here. And this allows the two [10:36] dies to communicate with each other at [10:38] 10 TB per second speed, making [10:40] essentially one functional GPU. And this [10:43] isn't like the first time this has been [10:45] done. You will often find the fact that [10:49] multiple dies are connected to make one [10:51] functional computation device when uh [10:53] the retical limit limits the the size of [10:56] the die that you can make. Okay. So this [10:58] is the with respect to the two dieseS [11:00] and then we have the HPM control which [11:03] is essentially the interface between the [11:04] high bandwidth memory which is where you [11:08] load memory into the into the GPU itself [11:10] whether it be model weights, activations [11:12] etc. [11:13] um and the graphics uh process clusters. [11:16] So essentially if we look back at this [11:19] diagram here, if you look closely, [11:20] there's eight HPM stacks on one GPU, [11:25] four on each side. And if we come back [11:27] here, you can see there's four HPM [11:29] controls making eight in total per GPU. [11:31] So u you can see precisely where this [11:34] maps on the actual uh GPU itself. And [11:38] let's talk a bit about what this HPM is. [11:40] So it's principally made by SKH Highix [11:43] for Nvidia, but Nvidia is also partnered [11:45] with Samsung as well as Micron. So those [11:49] are the three largest HBM manufacturers [11:52] in the world. And Nvidia uses all three [11:55] for its comput uh for its HBM and [11:57] compute needs. So there's not like some [11:59] single transaction going on here between [12:01] Nvidia and one of the providers. And [12:03] this is essentially vertically stacked [12:06] HPM. Specifically for the GB00, it's 12 [12:09] high HBM 3E. So what does that mean? It [12:13] means that there's 12 stacks of HBM that [12:15] are vertically stacked. And HPM 3E is [12:17] just the um the generation. So right [12:19] now, actually there's already HBM4. For [12:21] example, Samsung is producing HM4, which [12:24] as you can imagine has improved [12:27] specifications over HPM 3E, but for this [12:29] specific generation of GPU, that's [12:31] what's being used. And we can see here [12:34] that um there's 288 gigabytes of memory [12:37] per GPU with up to 8 terabytes per [12:40] second of data transfer. And right here [12:43] you can see the 12 high stacks. And if [12:45] we just come here and do 288 / 8, that [12:50] gives us 36 gigabytes per HPM stack. And [12:55] then if you divide that by 12, you [12:56] actually get 3 GB of HPM per layer. And [13:00] there's 12 layers. and it's 12 high. [13:03] Otherwise, you also have this gig thread [13:06] engine with MIG control and this stands [13:10] for um multi-instance GPU. So, that's [13:13] kind of cool. What it allows you to do [13:14] is essentially isolate and partition the [13:17] GPU into multiple instances to have kind [13:20] of like functionally a few separate [13:23] processes on the same GPU. So, um, if [13:26] you've heard of like on a virtual [13:28] machine or on a private cloud, you can [13:30] partition a server into multiple [13:32] different, uh, pieces for different [13:34] users, this is somewhat similar. And [13:36] then, um, just to finish this off, we [13:38] have the NV deck, which is the Nvidia [13:39] decoder. This is just for, um, decoding [13:42] videos. So, nothing too crazy here. One [13:44] thing is that I want to confirm the HPM [13:47] control um loads the model weights or [13:50] whatever uh memory you want first to the [13:52] L2 cache which is a faster bandwidth [13:57] memory than HBM but also more expensive [13:59] in terms of the memory density and then [14:02] you load that into the graphics process [14:04] cluster where the actual SM are the [14:06] streaming multiprocessors which contain [14:08] the the cores that CUDA uses in order to [14:11] actually perform computations and And [14:13] then another thing which I did not [14:15] mention earlier is that Envy link here [14:17] on the left is Envy link 5 which is [14:20] using the switch and this is connecting [14:23] one GPU to all other GPUs on the rack. [14:26] So if you have 72 GPUs they're actually [14:28] connected all to all. So you can send [14:30] any piece of data from one GPU to the [14:32] next with zero hops which is one of the [14:35] most um particular aspects of the Nvidia [14:39] rack scale systems. Whereas, for [14:41] example, if you have a TPU, you have [14:43] what's called in some uh terminologies a [14:47] dragonfly dragonfly topology where you [14:50] have like these TPU pods that are [14:53] connected in clusters and then you would [14:54] have to like hop between the clusters to [14:56] get to a second device or another device [15:00] that you want to send memory to. There's [15:01] pros and cons for all of these, but then [15:03] on the right we actually have Envy Link [15:05] COC, which stands for chip to chip. And [15:08] this is actually half the bandwidth as [15:09] NVLink V5. But what it is what it does [15:12] allow is to send um essentially data [15:15] from the GPU to the CPU directly which [15:17] avoids the PCIe which stands for [15:20] principal uh peripheral peripheral [15:22] component interconnect express. Um this [15:24] is actually 256 GB per second. So more [15:27] than three times slower than the TOC. [15:29] And because we uh do have this chip to [15:32] chip connection then uh we can avoid [15:34] using PCIe for any CPU to GPU. um [15:37] communication. So this brings us to the [15:42] uh the summary of this chip itself. And [15:44] then of course as I mentioned earlier [15:46] you have the fastest bandwidth on the [15:48] entire chip which is the uh well not on [15:50] the entire chip because the bandwidth of [15:52] the the L1 cache in the actual SM is [15:55] probably the fastest but um the 10 [15:57] terabyte per second between the dies is [15:59] also extremely fast and this is what [16:01] allows you to have two dieseS act as one [16:03] functional GPU. So, we've discussed the [16:06] chip on the low level. Of course, [16:10] there's lower levels, but that was [16:11] pretty in detail. Now, let's talk about [16:13] what happens when you're performing [16:15] inference. So, let's get this out of the [16:17] way or let me see here. Um, the title of [16:20] the the side here is that the model is [16:22] loaded once, but then each forward pass [16:24] reuses it from HPM. So, let's just go [16:27] through the the life of a model [16:31] inference call. So, first of all, you [16:35] will load the model at some point from a [16:36] model registry on the cloud or on the [16:38] network where the cluster is located. [16:41] And then this goes onto some local NVME [16:43] SSD, which is likely going to be on the [16:46] NVL72 rack. There's just SSDs for [16:49] storage like this. Then this would be [16:51] routed to the CPU, the Grace CPU, and [16:54] then feed it into HPM memory for storing [16:57] weights, KV cache, and activation. So, [16:58] this is a onetime load path as I said [17:00] here. Um but then when we're going into [17:02] the forward pass stage, well you have a [17:05] request that goes through the um [17:08] nick/dpu. So nick stands for once again [17:11] network interface card or data [17:12] processing unit to actually get to the [17:15] correct CPU which will handle [17:16] tokenization, queuing and batching which [17:18] are all like not really parallelizable [17:22] computations like the mat that we're [17:24] going to do in the GPU itself which is [17:26] in this box. So we go from the HPM [17:29] to the shared L2 cache once we have our [17:33] weights and if we've already done some [17:35] inference calls then um you'll already [17:37] have loaded the KB cache for the [17:39] previous keys and values that you've [17:41] computed and then from the L2 cache [17:44] the uh the model weights or whatever is [17:47] fed goes into the graphics process [17:49] cluster where there's the L1 cache that [17:51] feeds it into the SMS and then you [17:54] calculate logistics you get the next [17:56] token and And then um once this process [17:59] is done and you have like finished the [18:00] request, end of token is received uh [18:02] you'll propagate that back to where the [18:04] request was sent. And one thing that's [18:06] worth noting is that if you've heard of [18:08] the concept of cache hits, this is also [18:11] relevant for GPUs in the sense that if [18:15] you are performing next token prediction [18:18] and let's say that uh the SM has just [18:22] completed a single forward pass and has [18:24] now generated the next token and now it [18:27] needs the KV cache in order to perform [18:30] the next inference step. Well, depending [18:33] on where the KV cache has been loaded, [18:35] you'll get a certain cache rate uh a [18:38] cache hit rate. So, let's say that the [18:40] the KV cache is actually still in the [18:42] GPC in the L1 cache, then it'll be very [18:44] fast. The SM will just make one step [18:46] request to L1. Um it will essentially [18:48] check for a tag, which is like an [18:49] equality check to see is this value that [18:51] I want still there. If it is, it will [18:53] immediately retrieve it and then perform [18:55] the computation. Whereas, let's say that [18:57] the KV is on the L2, then it'll have to [18:59] take two steps, get to L2, and then send [19:00] it back to SM. Um, and in an even worst [19:03] case scenario, uh, if the model weights [19:06] and activations are stored on HBM, then [19:09] you'll have to go from the SM to L1 [19:11] cache to L2 cache to the through the HPM [19:14] control to the HPM and then go propagate [19:17] back down to actually send the data. So, [19:20] of course, this is all at the hardware [19:22] level where these um these cache [19:24] policies and protocols are specified. [19:27] And you can be assured that the Nvidia [19:29] uh RTL engineers are optimizing this [19:31] quite well. But it's a interesting thing [19:34] to note in terms of how fast inference [19:38] will be based on how well these um cache [19:41] hit algorithms and specifications are [19:44] created. So this is uh this is an [19:48] overview of what happens on a forward [19:50] pass for the chip itself. Moving on, um [19:55] we can kind of look at the industry on a [19:56] high level here, which is data from July [19:59] 2026. So just a month from this month in [20:02] August. First of all, I want to note how [20:05] many transistors are currently on a [20:08] GB300 Ultra. So across the two dies, [20:11] it's 28 billion transistors or 104 [20:14] billion transistors per uh die. And the [20:18] estimated cost of a 72GPU rack is $4 [20:22] million. So insane the cost on this. And [20:25] then $135 kilowatt, which is much more [20:29] than a single household consumes. And [20:32] then in terms of the industry overall [20:35] capex for this year, um projections were [20:38] in the like the 600 billion range in the [20:41] beginning of the year, but now it's um [20:43] around $800 billion of capex this year. [20:46] and projections going all the way to 1 [20:48] trillion for the year 2027. [20:51] I said 28 billion parameters here which [20:54] is impressive itself but if you consider [20:57] other uh semiconductors such as the [20:59] wafer scale engine on the Cerebrris chip [21:02] which you heard of Cerebrris it's a chip [21:04] that's optimized for extremely high [21:06] throughput compute and this is done by [21:09] having essentially all of the memory on [21:11] the silicon itself in SRAMM which means [21:13] that the the memory transfers are [21:15] extremely fast. That one has 4 trillion [21:17] parameters. Sorry. Yeah. 4 trillion [21:19] transistors, not parameters on a single [21:22] die. Um, and it's because it's literally [21:24] the size of of a wafer. And a wafer, if [21:26] you don't know, is 30 cm by 30 cm or [21:30] like a foot by a foot in imperial, [21:32] whereas um these Nvidia dies are [21:35] smaller. So, this doesn't mean that [21:37] Cerebras is definitely better. Um the [21:40] reason why we have 4 trillion on the on [21:42] the Cerebras chip and only 28 billion on [21:44] the Nvidia chip and the fact is that the [21:46] Nvidia chip is still overall still [21:49] better is because SRAMM for example [21:52] requires six transistors to store one [21:54] bit whereas HBM which we don't count in [21:58] the compute dies because the HBM once [22:01] again is not actually on the um is not [22:05] on the die itself. If we come back here, [22:06] the HBM is attached uh through the HPM [22:09] control on the shoreline, but it's not [22:11] actually on the die. Um the reason why [22:14] the HPM is because it is one one one [22:18] transistor and one capacitor per bit [22:20] versus six transistors per bit for SRAMM [22:23] which is used in the SEUS chip. And for [22:26] this reason, you have a much better [22:27] density. Um and the HPM is actually not [22:30] on the chip. So, all that is to say, we [22:32] can scale up to 4 trillion, but Nvidia [22:35] chips are in the 200 billion uh [22:37] transistor range currently. [22:41] And right now, we're going to talk about [22:43] Blackwell Ultra since it's more current [22:45] and it's the most prevalent latest gen [22:48] chip being deployed. Um, however, [22:50] there's the Ver Rubin uh generation [22:53] which is coming out has already actually [22:55] been tested. So Cory, for example, has [22:57] already deployed an a V an a VR NVL72 [23:01] rack uh in their servers as like a test, [23:05] but um as you can see here, shipments [23:08] are scheduled to begin in fall 2026 as [23:10] opposed to systems being available as we [23:13] speak for the Blackwell Ultra. And then [23:14] if you took look at the this a few of [23:16] the differences, for example, with the [23:18] Ver Ruben chip, you have HBM4, which is [23:21] just a the next generation. Once again, [23:23] this one is made by Samsung. I assume [23:24] that Skhanx will also be providing these [23:26] but I am aware that Samsung is providing [23:28] these currently to Nvidia. And then the [23:30] process note which you don't need to [23:32] know now but you just need to know that [23:33] the lower the number is the better is [23:35] the 3 nanometer process for TSMC for Ver [23:37] Ruben whereas it's the uh 4nm process on [23:40] the black wall ultra. So one step better [23:42] in that regard and then there's also [23:44] some differences in packaging which [23:45] we're not going to get into. However, [23:47] one thing I do want to mention that is [23:49] extremely new news is the fact that Vera [23:53] Rubin initially had a specific memory [23:57] allotment per GPU which I am forgetting [24:00] right now but all you need to know is [24:02] that currently it's not officially [24:04] disclosed but Nvidia is seriously [24:06] considering reducing the amount of HBM [24:09] per chip because of HBM shortages and [24:13] they just want to ensure that they can [24:14] make enough chips and not be bottleneck [24:16] by not being able to shuffle these chips [24:18] because they don't they can't get the [24:19] HPM. So that's one thing that's quite [24:21] interesting is that um the HPM that was [24:23] initially announced will likely be [24:25] reduced for the Vera Rubin generation. [24:30] And as we've already mentioned, we're [24:32] going to talk about the six stages that [24:34] create an accelerator through the course [24:36] physics, design, fab, memory, package, [24:38] data center. And we're going to start by [24:42] looking at how transistors work and also [24:46] why leading edge fabs cost more than $20 [24:50] billion and how the capex required for [24:53] these fabs is just becoming more and [24:55] more uh insane. And there's actually a [24:58] law similar to Moore's law which is [25:00] called rock's law actually which we'll [25:02] talk about that uh essentially [25:05] empirically predicts the cost of being [25:08] able to fabricate these leading edge [25:10] chips. So one thing that I want to first [25:13] um disambiguate since we already kind of [25:16] mentioned this earlier is the two [25:20] constituent components that at a high [25:21] level compose an accelerator. Um so we [25:24] have the logic which does the [25:26] computation at a high level and then we [25:28] have the HBM the high bandwidth memory [25:30] die which stores and is essentially used [25:34] for containing the model weights KV [25:37] cache etc. They optimize for different [25:40] things. So, of course, logic is based on [25:43] a timed driven network, which is to say [25:45] there is a clock cycle that occurs. And [25:47] this is just so that you can have [25:49] operations that occur in a synchronous [25:50] way and that can actually like [25:52] communicate with with each other. It's [25:53] like thinking, well, if there was no [25:56] like central concept of time, then the [25:58] world would probably be pretty bad [26:00] because like flights wouldn't even know [26:02] when to land. There would be no central [26:04] consensus on what time it is. So, it's [26:05] the same thing when you have a computer. [26:07] And one thing that I would like to [26:08] quickly mention is that the GB300 Ultra [26:12] GPU has a clock speed of 1.7 billion [26:16] cycles per second or 1.7 GHz. Whereas if [26:20] you know about CPUs, the best CPUs or [26:23] many CPUs can be clocked in the range of [26:26] 5 billion cycles per second. So three [26:29] times faster than a GPU. So naively one [26:32] would think well CPUs are therefore [26:36] three times better than GPUs. But let me [26:38] explain quickly why this is not the [26:40] case. So first of all a CPU has way less [26:43] cores and is mainly based on like doing [26:47] really fast sequential operations [26:49] whereas a GPU has many thousands of [26:52] cores that does parallel uh computation. [26:55] And one thing worth noting is that as [26:58] you increase frequency of a clock cycle, [27:01] of course you can do more computations [27:02] per second, but actually the power [27:05] required scales uh simply in simple [27:08] terms it scales cubically. So like the [27:11] more you want power um essentially the [27:14] the power curve increases as a cubic [27:16] function. So it means you need a lot [27:18] more power to have a faster chip. And [27:21] and what this means, if you actually had [27:22] like thousands of cores that were going [27:24] at 5 GHz, then the chip would literally [27:25] like melt. Um, and then furthermore, [27:29] even if you were able to get the chip to [27:31] work at 5 GHz, like a GPU at 5 GHz, all [27:33] these,000 cores, um, the problem is is [27:35] that the chips would be sitting idle the [27:37] entire time. Why is that the case? [27:39] Because currently the memory uh, [27:41] standard and state-of-the-art is just [27:44] simply not fast enough in terms of [27:45] bandwidth to satiate these chips to like [27:47] keep them busy uh, and doing [27:49] computation. If all these chips were [27:51] operating that fast, essentially if you [27:53] had chips operating this fast on a GPU, [27:55] they would just be doing computation for [27:57] like 1% of their time. This is of course [27:59] not precise, but they would be doing [28:01] computations very briefly and then just [28:04] waiting waiting because they're working [28:06] so fast until the next uh memory or [28:09] instruction comes into the register. So [28:12] this is just a quick digression on why [28:15] GPU clock speeds are slower than CPU [28:17] clock speeds. In any case, you have [28:19] standard cells, SRAMM on the chip [28:21] itself. So, this would be in the in the [28:23] different caches and also custom data [28:25] paths like the uh the SM which perform [28:29] matrix multiplications that are [28:31] optimized for speed and computation. And [28:34] then on the HRM DRM die, you have [28:36] billions of 1T1C cells. And what these [28:39] are are once again the one transistor, [28:42] one capacitor cells that can store one [28:43] bit of information. And this optimize [28:46] this optimizes for bits per millimeter [28:48] squared. And since really the HBM is [28:53] two-dimensional and that there isn't [28:54] that much restriction on how high you [28:56] can build, that's why you have HBM which [28:59] is now becoming threedimensional and [29:00] you're stacking it on top of each other [29:02] because we want to have memory density [29:05] increase. And there's only so much that [29:07] you can do in terms of increasing [29:09] density in a two-dimensional surface. [29:12] But you can do a lot more creative [29:14] things on three dimensions. One thing [29:16] worth noting though is that when you do [29:19] make HBM three-dimensional, not only [29:22] does it become more complex, but the [29:24] actual density becomes uh is reduced. [29:28] And one reason for this is because [29:31] essentially you need TSVs which stands [29:33] for through silicon via which are [29:36] literally like vertical holes through [29:39] these 12 stacks of high bandwidth memory [29:41] which facilitate data transfer between [29:43] the layers. And you can imagine right if [29:45] you have a hole going through the the [29:47] HBM then that space cannot be used to [29:49] store bits and that's one reason why 3D [29:52] uh stacked HBM is less memory dense than [29:55] 2D um DRAM. But this is a willing [29:59] trade-off because if you stack enough of [30:01] them then the overall density will be [30:03] increased. So there you have it. Logic [30:06] and DM optimize different constraints [30:08] but at a high level this is what [30:10] constitutes the the the acceleries that [30:11] we're going to discuss furthermore. [30:14] And a very crude um setting for what a [30:19] transistor is is essentially a gate [30:22] which has a source and a drain. So in [30:25] this case uh we know it's a source and a [30:27] drain because the the crude arrows here [30:28] are flowing from left to right where the [30:31] gate based on its voltage can turn this [30:34] path on or off. And essentially um we [30:36] can consider voltage a voltage reading [30:39] versus zero voltage or whatever the the [30:41] chip is tuned to as equivalent to a bit [30:44] being equal to one or a bit being equal [30:46] to zero. And billions of these switches [30:48] combined to store bits and perform [30:50] calculations. That is the only device [30:52] level idea we need for the rest of the [30:54] course. So you can rest assured that [30:56] we're not going to be going very deep [30:58] into the transistors. The only other [31:00] thing that we will discuss in a bit is [31:02] the actual number of uh the number of [31:05] types of transistors since this is what [31:07] you call a planer transistor because [31:09] it's flat. But there are a few different [31:11] types that especially to allow for [31:14] Moore's law to continue to uh advance [31:17] were created. One amazing fact about the [31:21] increase in transistor count which is [31:24] Moore's law is that it has increased 146 [31:28] millionfold from 1971 with the Intel 404 [31:32] to uh today with the Nvidia Reuben. That [31:35] actually has on the order of 336 [31:38] billion transistors. So in 55 years we [31:42] had a 146 millionx increase. But as I [31:46] mentioned before, the Cerebras wafer [31:49] scale engine 3, which actually is from [31:50] 2024. In fact, um the fourth generation [31:53] of Cerebras chips came out yesterday, [31:56] but I don't have the stats on those yet. [31:58] Um has four trillion transistors on one [32:00] wafer size chip, which is actually 50x [32:02] and H100. So um if we were being um [32:06] precise here, this should be slightly [32:09] bigger. And then how do we get from [32:12] 2,300 to 336 billion? Well, there's two [32:15] ways. You either add more silicon, but [32:19] above all, uh you make the process [32:23] denser, which is to say you make the the [32:25] the transistor the gates smaller and so [32:28] on. And another cool fact here is that [32:31] if you counted one transistor per [32:33] second, this uh Intel 40004 would only [32:36] take 38 minutes to count, whereas the [32:39] Nvidia Reuben would take 10,000 years to [32:42] count every single transistor. So I said [32:44] a few slides ago that we don't need to [32:46] worry about what a process means. But [32:48] now we're going to talk about process [32:49] nodes to clear that up. So right now for [32:52] example TSMC's one of their latest [32:55] process nodes is the 2nm process. And [32:57] naively you'd think that this like is [33:00] equivalent to some measurement on the [33:01] chip itself. But this is not actually [33:04] the case. It's not a feature. It's [33:06] simply a label that bundles the [33:08] transistor architecture, wiring stack, [33:10] design rules, materials, and libraries. [33:11] So you can kind of think of it as like [33:12] the iPhone 10. The 10 doesn't really [33:15] mean anything in terms of like there [33:17] isn't 10 parts of it. It's just the [33:19] generation name, right? Um so this is [33:20] the similar setup for process nodes for [33:23] semiconductors except a long time ago or [33:27] sometime before the year 2000. Um the [33:31] the processes actually represented the [33:34] pitch of the transistors which is to say [33:36] like the distance between consecutive [33:38] transistors. But um because Moore's law [33:41] essentially started to uh stagnate at [33:44] least in terms of the density of [33:46] transistors. So of course there were [33:48] other things that occurred to allow [33:49] Morsaw to persist but in terms of just [33:50] like making the transistors smaller and [33:52] smaller. This did lead to diminishing [33:54] returns. Um they still started [33:57] decreasing the name of the nanometer. So [33:59] before it would have been like the 10 [34:00] micrometer process etc. But at a certain [34:02] point it no longer compos it it no [34:04] longer was equivalent to the transistor [34:07] pitch which is once again the distance [34:08] between consecutive transistors and [34:10] simply became the name for the [34:12] generations. So to repeat the 2nmter [34:16] process node is just like a TSMC Taiwan [34:18] semiconductor manufacturing company name [34:20] for their generation of semiconductor [34:23] not an actual measurement on the on the [34:24] chip itself. And because this metric [34:27] doesn't actually tell us anything about [34:30] what has changed from generation to [34:32] generation, there's instead a industry [34:34] cited criteria which is PPA which stands [34:37] for power, performance and area which [34:39] are the three ways a design gets better. [34:42] So power which is to say um how many [34:44] watts under a state of workload are [34:46] required to do some piece of work. [34:48] performance can think can be uh per [34:50] throughput or latency and then area is [34:53] like the actual silicon that is [34:54] occupied. So if you look for example at [34:57] TSMC N2 versus N3 um at the same power [35:01] it's 10 to 15 time 10 to 15% faster or [35:04] at the same speed it uses 25 to 30% less [35:07] power and then if you consider the area [35:09] axis it has 15% greater chip density on [35:13] the same amount of area. So this kind of [35:15] explains how each of the three criteria [35:19] that we're talking about when we go from [35:20] one node to the next differ. Okay. So [35:23] we've discussed how trans transistor [35:26] generations improve or rather differ [35:28] from one to the next. Now let's talk [35:30] about three different geometries which [35:32] are three of the most prevalent. Um the [35:34] first one being planer in the bottom [35:35] left you can see and this is just a [35:37] blown up version of the diagram that we [35:40] saw earlier. So just to jog our memory, [35:42] this is the same thing as this right [35:44] here where the source on the left and [35:46] the drain on the right. Essentially this [35:48] this dictates the direction that the [35:51] electrons move. And this is a [35:53] cross-section of the channel itself. And [35:57] here you have the channel length and [35:59] this is called the gate. And essentially [36:02] as transistors became smaller and [36:03] smaller then the L was reduced right the [36:08] channel length must become smaller if [36:10] you want the transistor to fit into a [36:13] smaller space. And just to remind you [36:16] guys essentially the gate is what is [36:18] controlling the channel that it applies [36:21] voltage to the channel which controls [36:23] whether or not the switch is on or off. [36:25] Um the problem is that as you reduce [36:27] this channel like quantum effects [36:29] literally quantum effects make the gate [36:31] control weaker which means that there's [36:33] more I off and I off just means I stands [36:37] for current and off means that there's [36:39] more current even when the gate is off [36:41] which essentially is off state electron [36:43] leakage and that's not good right if you [36:46] want your gate to be reliable and not [36:49] consume a lot of power then it must be [36:53] uh following what the gates It says so [36:56] given this problem engineers had to look [37:01] into uh different solutions because more [37:04] electrons leak from source of drain as [37:07] channel length shrinks. And in the next [37:10] slide we have the first approach which [37:14] was very successful in addressing this [37:15] problem. And this is called the finfet [37:18] or fin field effect transistor or a [37:22] trigate. And it's called the trigate [37:24] because the gate is essentially like [37:25] three pieces. Um but I like to think of [37:27] it more as a finfet because it looks [37:29] like a shark fin. So essentially this is [37:31] once again a cross-section. So whereas [37:33] here the current was flowing from left [37:35] to right, it's actually better to [37:36] visualize the finfet as the current [37:38] flowing into the page or out of the page [37:40] whichever way you like. So you can think [37:42] of the finfet as cut like this as [37:44] opposed to this um in the other diagram. [37:47] And the channel is literally giving us [37:50] the current into our face. What what's [37:52] the reason that we have this? Well, the [37:55] fin fet right it raises the channel into [37:58] a vertical fin. So the gate controls the [38:02] top and both sides which improves the [38:05] ability to uh reduce leakage. And just [38:09] for history sake, Intel announced its [38:11] 22nm finfet in 2011 and shipped in 2012. [38:15] So we're talking uh like uh a decade and [38:18] a half ago when this innovation was [38:20] made. So this was the first way that [38:22] electron leakage was addressed. And the [38:26] third and final one is even cooler and [38:28] even more recent. So was put into [38:30] production in 2022. And let's see what [38:32] it's called. It's called the nano sheet [38:35] or stacked nano sheet. So the stacked [38:37] meaning you have multiple channels [38:39] stacked on top of each other gated all [38:41] around. And the name is actually [38:44] self-explanatory. You have this gate and [38:45] it goes all around each channel. And [38:48] once again here we have the transverse [38:51] cross-section with the currents coming [38:53] into or out of the page sitting on this [38:55] silicon substrate. And with the fact [38:57] that the gate goes around the top, [38:58] bottom and sidewalls of each seat, the [39:01] electrostatic control allows you to [39:03] continue scaling uh channel reduction [39:07] and the sheet width. So the width of [39:10] these pieces actually gives designers [39:12] another way to turn tune the current [39:14] that is passing through uh these [39:16] transistors. So once again this was the [39:19] first process uh node to use this gated [39:22] allaround the Samsung 3 nanometer [39:24] process and one thing worth noting is [39:27] that actually in production ramp up or [39:29] production hell because it was hard the [39:31] yield which is like how many of the [39:33] chips are actually usable was 50 to 60% [39:36] with these gated allaround for Samsung [39:37] which is quite low uh you'd want it to [39:39] at least be in the 70s to 80s to have [39:41] good profit margins and what this meant [39:42] is that a lot of Samsung uh customers [39:45] like Qualcomm were actually not willing [39:47] to move on as this process node because [39:49] of the worry for lack of reliability. So [39:51] Samsung actually had to use this and [39:53] essentially dog food it which means use [39:55] it internally uh because of course [39:56] Samsung makes their own devices and this [39:58] allowed them to still use the node [40:00] commercially because external users were [40:02] not willing to use it but they were um [40:04] so 2023 was a pretty tough year for [40:06] Samsung but um by now 2026 they have [40:10] been able to get process node [40:13] fabrication with the gated allaround [40:15] under control and we're going to talk [40:16] about this later but it's interesting [40:18] because TSMC which of course is the most [40:21] advanced fabrication company for [40:24] semiconductors in the world hasn't [40:26] actually yet introduced these at mass [40:28] scale and once again this is because of [40:30] the complexity of processing and [40:32] creating these transistors you can [40:34] imagine just by like looking at the [40:35] images right the planer is the simplest [40:37] the finfed is more complex and then the [40:39] gate all around is the most these aren't [40:41] the only three types of transistors of [40:42] course but these are three uh flagship [40:44] transistors that are worth knowing about [40:46] so you've definitely heard of Moore's [40:48] law which talks about the density [40:50] density of transistors on a [40:53] semiconductor. However, Dennard scaling [40:56] is a similar law which said that as [40:58] transistors got smaller, the voltage [41:01] required to power them actually dropped, [41:03] keeping the power density roughly [41:05] constant because of course you had more [41:07] transistors. But if the voltage required [41:09] to power the individual transistors [41:11] drops, then you can have this [41:12] equilibrium. But this ended because [41:15] voltage stopped falling fast enough to [41:17] keep power density flat. And this [41:20] occurred in the 2004206 range when the [41:24] power all was hit and frequency scaling [41:26] stalled. So essentially what this meant [41:28] is that it was no longer possible to [41:30] trivially increase the frequency which [41:32] is to say the clock speed of the CPUs [41:34] because of the power required and the [41:37] thermal heat that would be generated by [41:41] having chips run at such a speed. And [41:43] therefore, designers spent new [41:45] transistor budgets on multiple cores and [41:47] parallel accelerators, which of course [41:50] makes GPUs more important eventually, [41:51] but also overall just means that instead [41:54] of making purely denser transistor [41:57] counts, we also now split up our [41:59] computation parallelly, which is once [42:02] again what kept Bourne's law going. And [42:04] now to go back to the law I mentioned [42:07] called rock's law which states that a [42:12] fab for semiconductors must double every [42:16] four years in terms of the cost required [42:18] to essentially produce the latest [42:21] generation chips. Um you can say this [42:23] empirical law means that from the 1970s [42:26] it would only cost $4 million to be [42:28] processing the latest node the latest [42:29] gen semiconductors whereas now in the [42:31] 2020s it's in the 20 billions and for [42:34] people like uh TMSC it's somewhere [42:37] around 50 billion uh the number we'll [42:39] talk about in precise detail later in [42:42] the course of course this is a log scale [42:45] graph right so don't just think that [42:47] these are like linear proportions and in [42:50] fact you can see that the cost 5000X [42:53] since the early9 1970s and the companies [42:56] the leading edge from 13 sorry 130 [42:59] nanome to 2 nanome so across these [43:02] generations went from 25 to three and [43:05] these three are Samsung, Intel and TSMC [43:07] the current uh leading edge fabricators [43:11] of semiconductors. Interesting to note [43:13] is that for example in Japan there's a [43:15] government effort to make their own [43:18] government sponsored leading edge fab [43:21] but that has not yet reached its goal [43:23] that is supposed to happen in 2027 and [43:25] then also there's smick in China which [43:27] is also leading their own effort but as [43:29] of today there's only three leading edge [43:31] fabs because of the cost required to [43:35] keep up with the latest technology and [43:37] the latest research and what this cost [43:40] increase meant was that in my terms the [43:44] great unbundling occurred which [43:46] essentially just means that design split [43:49] from manufacturing when the factory [43:51] became too expensive for one product [43:54] line. So if we go back a really long [43:57] time ago in 1971 Frederrico Fagen who [44:00] was the Intel 40004 architect literally [44:04] drew the 2300 transistors for the Intel [44:08] 40004 by hand on paper. You can find the [44:11] piece of paper where the layout is [44:12] online. And this was quite simple, [44:16] right? This didn't require $20 billion. [44:18] But as complexity and fab cost exploded, [44:20] design and manufacturing became distinct [44:22] businesses. And the foundry model [44:25] essentially lets design lets designers [44:27] like TSMC pull their demand from many [44:29] customers such that they don't also have [44:32] to have the onus of creating chips that [44:34] create enough revenue in order to keep [44:36] up with the next process node. And to [44:39] reiterate, we're pooling demand across [44:42] many chip designers as a TSMC such that [44:44] the chip designers pay for the wafers, [44:46] not an entire factory. One example of a [44:48] chip designer being Nvidia. And then the [44:50] the foundry is able to combine these [44:51] orders across many customers and spread [44:54] the fixed costs across many different [44:56] wafers, making manufacturing itself a [44:59] product instead of manufacturing the [45:02] devices as the only business. So [45:05] fabulous firms were literally b born out [45:07] of this. Um Nvidia being an example of a [45:10] fabulous firm meaning that they don't [45:11] actually have their own fabricating [45:12] plants, right? It's TSMC that's taping [45:14] out the ships for them and they can [45:17] spend all their time in contrast now on [45:19] design and products rather than [45:20] financing the factories. So this kind of [45:22] biodal split seemed to benefit both [45:26] sides at the expense of having no more [45:30] really integrated manufacturers apart [45:32] from Intel and Samsung who are still [45:34] doing both both sides of the coin. But [45:37] um we may see that this stops in the [45:39] future if the TSMC model continues to [45:42] succeed. So as of today there are four [45:45] main business models in the [45:46] semiconductor industry. As I mentioned, [45:48] the fab model where you design chips and [45:50] contract with founders, Nvidia, [45:52] Qualcomm, AMD, Apple and Apple Silicon [45:55] being examples. Of course, Apple silicon [45:57] may be moving to Intel now, which is [45:59] interesting. Then you have the Foundry, [46:02] which is who manufactures chips designed [46:05] by its customers, TSMC being the main [46:07] one here. And then you have the IBM, [46:09] right, which is the integrated device [46:11] manufacturer or sorry, integrated device [46:13] manufacturer, which designs and [46:15] manufactures shifts. So, Intel, Samsung, [46:17] and a few analog suppliers being the key [46:20] examples here. However, it's worth [46:21] noting, right? Intel and Samsung both [46:23] make chips and other devices for other [46:25] people as well. Their only business is [46:28] not to make and sell their own devices. [46:30] For example, Samsung makes memory for [46:32] other companies. And then Intel also [46:34] makes chips for Nvidia, for example, for [46:36] some of their um rack, scale, compute, [46:40] and uh GPU platforms. And then finally [46:43] we have the the equipment business model [46:45] which is very critical here which [46:46] essentially supplies the tools used by [46:48] fabs. One of the two or two of the most [46:51] well-known names here are ASML here and [46:54] applied materials. So ASML making these [46:57] extreme ultraviolet lithography machines [46:58] which we'll talk about in detail and [47:00] applied materials making a whole bunch [47:01] of machines uh that manufacturers need [47:05] regardless of who is designing the chip. [47:08] Okay. So stage one really kind of laid [47:11] the foundation, described a few [47:12] transistor fundamentals, how the [47:14] business model works, and now we're [47:16] going to get into more detail [47:17] specifically on chip design from [47:19] architecture and electronic design [47:21] automation software to a manufacturable [47:24] design file that you would send as [47:27] people joke through um a FTP, a five [47:31] file transfer protocol from Santa Clara [47:33] where Nvidia is all the way to Taiwan. [47:36] And then that is essentially the final [47:37] product of Nvidia which is making them [47:40] billions of dollars. So we actually have [47:43] a diagram here of the entire uh [47:46] semiconductor industry. So we'll see [47:48] this in a big form at the end of the [47:50] course but for now we're focusing on the [47:52] design component of this industry as [47:55] we've already done the physics. So let's [47:57] uh jump right into it. So, since we're [47:59] talking about design and we promised [48:01] that this course is following the [48:03] Blackwell Ultra GB300 GPU, let's talk [48:06] about what actually the design looks [48:09] like at a high level. We talked about [48:10] like kind of like the memory placement [48:12] and what goes where in terms of the [48:15] physical layout, but we did not give a [48:17] treatment to the actual logic and how [48:20] it's organized. So a single GPU on a [48:25] GB300 has 16 has 160 streaming [48:29] multipprocessors [48:30] and these are physical compute blocks [48:34] which each one is composed of four [48:37] tensor cores. So this means that there's [48:39] 640 tensor cores per GPU as well as 128 [48:44] CUDA arithmetic lanes per SM. And if you [48:47] do 128 times 160, you get 20,480 [48:52] CUDA arithmetic lanes. Um, this is much [48:54] more than a like 16 core CPU. So now you [48:57] can see to what extent a GPU has more [49:00] cores for parallel computation. And once [49:03] again, these SM are actually split [49:05] across two dieseS connected via the [49:07] Nvidia high bandwidth interface. So why [49:12] do GPUs work for AI to begin with? Let's [49:15] motivate this really quickly. So it's [49:18] because with these matt moles that you [49:20] use for transformers and other neural [49:22] networks, the same math repeated across [49:25] many outputs. So like let's say you have [49:27] some activation which are the inputs to [49:30] a layer of the neural network as well as [49:33] uh the weights themselves. You can split [49:36] this job across many different [49:39] processing units and essentially have [49:43] many physical blocks doing work that is [49:44] independent and that is then aggregated [49:47] afterwards via theuler. But of course [49:51] parallelism is not unlimited. um [49:54] reductions within a specific tile and [49:56] dependencies between layers, branches, [49:59] uh memory bandwidth and communication [50:02] constrain to what extent you can utilize [50:04] all of the different cores of a GPU. And [50:07] uh this is quite important, right? If [50:09] you have heard of the the term [50:11] arithmetic intensity, this is [50:14] essentially the ratio of the amount of [50:17] compute that you're doing with respect [50:19] to the memory that you're transferring. [50:21] And you want the arithmetic intensity to [50:23] be sufficiently high to justify using [50:25] all of these cores. Um, and this is just [50:27] done through good software engineering [50:29] to take full advantage of the different [50:32] uh cores and SMS that the GPU has to [50:35] offer. So this is why for example CUDA [50:37] engineers make so much money. And [50:39] speaking of CUDA, this is what turns the [50:41] GPU into a software platform with more [50:44] than 6 million developers. Uh, of course [50:46] it was developed beginning in 2006 and [50:48] has returned a lot for Nvidia as a [50:52] software programming interface. It [50:54] allows you to expose the parallel [50:57] hardware of the GPU to software. There's [50:59] many libraries now if you've heard of [51:00] KUDNN and and so on that supply tuned [51:04] routines essentially kernels for AI and [51:06] math communication and the developmental [51:09] tools are also very refined. So with [51:11] respect to compilation, debugging, [51:12] profiling and deployment because of how [51:15] mature this ecosystem is and one thing [51:17] that is important right is that a [51:19] competing accelerator must support the [51:21] code and workflows teams already use [51:23] which in the case of CUDA is pretty deep [51:25] moat since um it's such a it's such an [51:27] integrated ecosystem of software. And [51:30] switching gears here now back to fabidia [51:33] supplies the design TSMC and the memory [51:35] makers supply the physical chip. So here [51:37] you have a crude layout here that would [51:40] actually be a electronic file not an [51:43] actual blueprint which is then turned [51:45] into these GPU dies that is combined [51:47] with memory in order to package it onto [51:50] into a SOC which just means system on [51:53] chip and this shows how a completed [51:56] accelerator depends on several [51:57] manufacturers even though Nvidia [51:58] consorts the product and this is only [52:00] the tip of the iceberg of how many fac [52:02] manufacturers are involved in creating a [52:05] GB300. We'll talk more and more about [52:07] the different parts of the ecosystem [52:10] which eventually support the creation of [52:12] these massive GPUs and to talk about [52:16] like the success of Nvidia. Um in the [52:19] full year in the full year 2026 they've [52:22] projected $215.9 billion in revenue with [52:25] a reported although not confirmed uh [52:28] gross margin of 71.1% [52:30] across their entire supply chain and the [52:32] margins on their AIA accelerators is [52:36] definitely higher than this but this is [52:38] the entire ind the entire uh company's [52:40] margins and uh according to Q2 estimates [52:44] from the industry 90% of all AI [52:48] accelerator revenue belongs to Nvidia [52:50] right now which is just absolutely [52:52] diabolical. Uh but this also means that [52:55] of that 10% this is essentially fighted [52:58] over by all other people in the space [53:01] and that's why you have so many new [53:02] generation semiconductor companies that [53:05] are trying to take a share of Nvidia's [53:07] dominance in the AI accelerator space. [53:10] So now we've talked about Nvidia and its [53:12] fabulous design. Let's go into the [53:14] software behind chip design which is not [53:16] based on Nvidia. Instead, we have a few [53:20] electronic design automation [53:22] manufacturers. This is the software that [53:24] engineers used to turn a chip [53:25] specification into a manufacturable [53:28] layout. And since modern accelerators [53:31] contain billions of transistors and many [53:32] layers of wiring, this is far beyond [53:34] what a team could place and check by [53:36] hand. Of course, this software extracts [53:39] quite a lot of the low-level design so [53:42] that um fabs like and fabous designers [53:44] like Nvidia can make a design which is [53:47] tractable to make every single year for [53:50] every generation to send to TSMC. Um [53:52] actually let's talk about the core [53:54] electronic design automation flow [53:58] which is to say how does RTL become a [54:00] manufacturable chip? So RTL just means [54:02] register transfer level which kind of [54:05] describes the software at the hard sorry [54:07] not sorry at the software but describes [54:08] the chip at a sufficiently low level in [54:11] the hardware where you have like these [54:13] gates like nan gates etc. Um it's [54:16] actually written in system vary log [54:18] mostly in the industry that's the name [54:20] of the HDL the hardware description [54:22] language used to describe chip behavior [54:24] and then you have the logic synthesis [54:27] which converts this register transfer [54:29] level into a gate level net list. So I [54:31] actually kind of misspoke here. The [54:32] engineers are actually not describing [54:34] the actual gates themselves. It's [54:36] slightly higher level. But then the [54:37] logic synthesis is what gives you uh the [54:39] gate level abstraction in this logic [54:41] synthesis. Then what you have is [54:44] hardware emulation/verification [54:46] which tests the behavior before it's [54:48] taped out into physical silicon. And [54:50] then moving on to physical design, you [54:52] place and route the gates uh that were [54:55] created through logic synthesis into a [54:57] layout of transistors. And then based on [55:01] the [55:02] fab that you're sending the uh design [55:05] to, you do the physical verification and [55:07] sign off, which is say like check the [55:08] rules, timing, power, and tape [55:10] readiness. Um, it's very interesting [55:13] because let's say that a a customer like [55:16] Nvidia is using Intel and TSMC to make [55:21] their own GPUs. Let's say [55:24] hypothetically. Well, even if they had [55:25] the same design, they would have to [55:28] essentially create the layout [55:29] differently for the two fabs because [55:32] Intel and TSMC have different ways of uh [55:36] manufacturing semiconductors simply. And [55:38] because of this, they can't just send [55:39] the same file and get the same thing [55:41] out. Um it's very dependent on who is [55:43] actually making the chip itself. So with [55:47] respect to how much this costs, a large [55:51] 2nm chip can cost about $725 million to [55:55] develop from scratch based on some [55:56] industry estimates, including 340 $314 [56:00] million for the software development and [56:02] $154 million for verification. Uh this [56:04] is why you see these new generation [56:07] semiconductor companies like etched [56:10] raising like a billion dollars or more [56:12] because of the intense upfront cost to [56:14] design these chips and even them they're [56:16] on a 4 nanometer process node so it's [56:19] much cheaper than 2 nmters in any case [56:21] it's still very expensive. Um these [56:24] estimates though are green field which [56:25] essentially means that it does assume no [56:27] reli reusable IP or product design [56:29] platform. Um and it's the total [56:32] development cost. It's not just a [56:34] licensing bill. Uh so like Nvidia is [56:37] definitely not paying this much for a [56:39] single chip, but at the same time since [56:40] they have so many engineers, maybe they [56:42] are. Of course, these numbers are not [56:43] public, but um these are the estimates [56:46] from IBS on the amount of money that [56:50] would be needed to make one of these [56:51] chips from scratch. So who is Nvidia [56:54] paying to use this software that does [56:56] the logic synthesis and the emulation, [56:58] etc.? Well, there's three big players [56:59] here among others. There's Synopsis and [57:02] Cadence which are both based in Silicon [57:04] Valley and there's Zemen's EDA which is [57:08] a German company. So let's start off [57:11] with Synopsis that was founded in 18 [57:13] 1986 and was the early leader in logic [57:15] synthesis. So this is once again if we [57:18] come back here the step where you can [57:20] convert the RTL into a gate level net [57:23] list and they're also provi they also [57:27] provide a lot of robust software for [57:28] digital design as well as semiconductor [57:30] IP. A big acquisition they did was [57:32] another EDA provider called ANCIS for [57:35] almost $35 billion in 2025. That's a [57:37] very massive acquisition. Uh then we [57:39] have Cadence which is also like another [57:40] big player here founded in 1988 2 years [57:42] later and their strongest suit is analog [57:44] and custom design. So they have this uh [57:47] platform called Virtuissu and the [57:50] hardware emulation software Palladium [57:52] which are ele emulators that run [57:54] pre-silicon designs at up to 48 billion [57:56] gates. So you can essentially simulate [57:59] what the gates are going to do [58:00] physically through this emulator in [58:02] order to determine if there's like any [58:05] fun any flaws. Of course, the the way [58:08] that these chips are verified and [58:09] emulated is extremely sophisticated, but [58:12] um this is one of the most important [58:13] steps because tape out actually turning [58:15] a design into silicon is extremely [58:17] expensive. If you mess it up, then that [58:19] will cost you very high uh fees to get [58:22] it fixed. So, instead, you want to pay a [58:24] lot upfront to get this emulator to [58:26] verify your design instead. And if you [58:28] look at companies like Nvidia, they're [58:31] very good with essentially having a [58:34] design that succeeds on the first tape [58:36] out without the need to go back and [58:38] forth with the fab. Whereas companies [58:40] like Intel historically have had issues [58:42] with having to do multiple tape outs to [58:44] correct issues that were only found once [58:46] the the semiconductor was made [58:48] physically. Then uh Seaman's EDA is the [58:51] third player in the space with 13% [58:53] market share. It has a product called [58:54] Caliber that's widely used for physical [58:56] verification and signoff. And once [58:58] again, this is when you compare the chip [59:00] design itself to what the FAB has in [59:03] terms of their process manufacturing. [59:06] And you do you do this in order to [59:09] verify that it's compatible with however [59:12] the [59:14] manufacturing process is for Intel, [59:16] Samsung, TSMC, whichever fab you're [59:18] using. [59:20] And what is the size of this market? [59:22] It's a $21 billion market. Um, and the [59:25] broad one other broad term that's used [59:26] is ESD, which stands for electronic [59:28] system design with Synopsis having the [59:30] most revenue of of all the players at [59:32] $7.1 billion. But interesting [59:34] interestingly, Cadence having the [59:36] highest margins at 86%. So, because they [59:39] have a much higher gross margin, they're [59:41] actually only 1% behind Synopsis even [59:43] though even though the contrast in the [59:45] revenue is much greater than the uh [59:47] market share. So, that's an interesting [59:50] thing to note. And then as we mentioned [59:51] before, Synops Seaman's EDA is in third [59:54] place at 13%. So if you add these up, [59:57] you get 61 + 13 giving you 74%. So [60:01] there's a another quarter of the [60:02] industry that is dominated by the other [60:04] small players. But these three players, [60:07] C, Synopsis, Cadence, and Seammens are [60:09] the three uh players that take up 75% of [60:12] the entire electronic system design [60:14] market. And this brings us to the first [60:16] checkpoint, which is essentially the the [60:19] choke point. Sorry, not the checkpoint. [60:21] That that means like if this industry [60:23] were to disappear tomorrow, then the [60:27] entire semiconductor industry would be [60:31] ineffective and they would be no no [60:32] longer a way to make semiconductors. Uh [60:35] and this is because synopsis and cadence [60:36] dominate the certified tool chains used [60:38] for leading edge chip design. Losing [60:40] access would delay advanced designs [60:42] because engineers have few substitutes [60:43] for critical steps and qualification for [60:46] these types of software takes years. So [60:48] this is one of the seven choke points [60:49] that we'll discuss. The first one in [60:51] fact and we'll keep on going throughout [60:52] the video to determine what are the [60:54] other critical components of the [60:57] semiconductor supply chain. So because [61:00] this is a choke point it is also exposed [61:03] to export controls. So this is a [61:04] patternable note throughout the entire [61:06] video. I I can already just jump ahead [61:08] to like lithography which is what you [61:10] use to actually like pattern the [61:12] silicon. That's another choke point [61:14] which is affected by export controls as [61:16] well. But jumping back to the electronic [61:18] system design field, um the few export [61:21] controls that have occurred in the past [61:23] were in 2022 when the US restricted EDA [61:26] software designed uh designs for the [61:29] GAA, so the gated all-around uh field [61:32] effect transistor development. And then [61:34] in May 2075, the Department of Commerce [61:37] imposed license requirements on most EDA [61:39] sales to China. But this only last for [61:42] like this only lasted for 6 weeks before [61:44] they lifted it because China actually [61:46] restricted uh gallium and German [61:49] germanmanium exports if I'm not mistaken [61:50] to the US and then this retaliatory um [61:54] uh tariff or rather export control made [61:57] it such that the the US was forced to [61:58] lift the the restriction because they uh [62:02] must not have their own domestic source [62:04] of these two rare earth minerals. So [62:07] this is the current state of affairs of [62:09] the EDA export control. So definitely [62:12] not as intense as a few other industries [62:14] which we'll discuss but still under the [62:17] watch of the US and Chinese governments. [62:20] And now if we zoom in here to design, [62:22] we've discussed electronic design [62:24] automation as well as fabas or we'll [62:26] discuss this in further detail but we've [62:27] gone through Nvidia at least. But before [62:29] we get to fabas in detail, let's talk [62:31] about intellectual property which is [62:34] highlighted by both ARM which is a [62:36] company and risk 5 which is a [62:38] instruction set architecture. So what [62:41] does that mean? An instruction [62:43] architecture defines the commands that [62:45] software can give a processor such as [62:47] like load, add, branch, um, move memory, [62:51] etc. Um, and ARM is one of the companies [62:54] that sells this IP on how you can define [62:57] this architecture. Um, and this is done [63:00] through selling CPU designs. And then [63:02] there's another architecture like risk [63:04] 5, which is an open set that anyone can [63:06] use to implement. Although it's [63:09] definitely not as easy to just trivially [63:12] take the risk five instructions set [63:15] architecture and make a CPU as we will [63:17] explain shortly. Um so focusing first on [63:20] ARM uh the essentially profit model that [63:22] they run is royalties on each chip [63:24] that's shipped with a typical rate being [63:26] between 1 and 2% on the chip's selling [63:28] price. They've produced up to three uh [63:32] up to date more than 350 billion chips [63:34] with their with their IP and 99% or more [63:39] of smartphones run ARM. The reason why [63:42] smartphones in particular are all in ARM [63:43] because it's much more energy efficient [63:45] than competing architectures. The main [63:47] one being x86. And since smartphones [63:50] have a restriction on the battery size, [63:53] then it is the uh far and away winner in [63:56] terms of uh smartphone and mobile use. [63:59] So once again, ARM licenses CPU designs [64:01] and architecture. Most contracts include [64:03] an upfront fee and then a purchip [64:04] royalty. And like everybody uses ARM, uh [64:07] so Apple does, Qualcomm, MediaTek, uh [64:10] there's also Nvidia CPUs. So the Grace [64:13] CPU that we mentioned actually has ARM [64:15] cores in it. And this 1 to 2% royalty [64:17] across billions of units means that with [64:19] broad adoption, there's a healthy amount [64:23] of recurring revenue for ARM. I'm not [64:24] sure what their profit margins are, or [64:26] their gross margins rather, but they [64:27] must be very high. And although I [64:29] mentioned that ARM mainly is in the [64:31] field of IP, which is to say licensing [64:33] finished CPU cores or the instruction [64:36] sets for a custom core, they are also in [64:38] the compute subsystem field, which is to [64:40] say a more complete integrated platform [64:43] instead of just the blocks that are [64:45] assembled from the IP. And lastly, [64:48] actually in physical silicon. So ARM [64:50] silicon which was announced in March [64:53] 2026 are its own AGI data centered CPUs [64:58] that are made by ARM AGIS. I think [65:00] that's the new department that makes [65:02] these uh silicon chips. And it's the [65:05] first production silicon product in [65:06] company history. In fact, as you can see [65:09] here, the reported AGI CPU demand [65:12] exceeds $2 billion across the fiscal [65:14] year 2027 2028. Um, and then selling [65:17] silicon also brings ARM closer to its [65:19] licenses, which is to say kind of [65:21] putting them in competition. So, we'll [65:22] see how this plays out because now the [65:24] companies that license ARM technology [65:27] are going to be competing with ARM [65:28] itself that's now making its own CPUs. [65:32] So, now going back to the open standard [65:33] that's actually made by Berkeley. So, [65:35] Berkeley is the university in the Bay [65:38] Area which actually maintains the risk 5 [65:40] standard. It's deployed at scale. In [65:42] fact about 1 billion cores a year are [65:44] shipped by Nvidia inside its GPUs and [65:47] it's used for example in storage [65:49] controllers, microcontrollers and [65:51] internet of think products and also [65:53] Nvidia embedded systems with controlled [65:55] software stacks make use of risk 5. So [65:58] it does make the instruction set free as [65:59] we've said here, but you must still [66:01] design and verify a core or license one [66:03] from a vendor. And this requires either [66:05] many many hardware engineers or to [66:08] actually still license it to another uh [66:11] hardware design firm that will actually [66:13] create a core from the instruction set [66:16] architecture. And once again, an ISA [66:18] just is defining the different primitive [66:20] com uh operations that the CPU can [66:23] complete. And for example, when we look [66:25] at commercial adoption, there's actually [66:26] no meaningful commercial smartphone [66:28] share in risk 5. There are a few [66:30] Chromebooks actually that are being made [66:31] with risk 5, which is quite cool. Um the [66:33] servers as well are limited on risk 5 [66:36] and it's one of the main ris and one of [66:40] the main issues that is leading to this [66:42] limited adoption is um software [66:44] compatibility. That's a big barrier [66:46] because these ecosystems are so [66:47] entrenched in the status quo that a new [66:51] ISA must compete with all of this [66:53] builtup knowledge and technology that's [66:57] based on other architectures. So now [66:59] we're going to jump into fabulous [67:01] manufacturing as promised which I would [67:03] split up into three categories that are [67:07] relatively loose. So for example, you [67:08] have merchant chips which are standard [67:10] products sold to many customers such as [67:12] Nvidia which makes its own AI [67:13] accelerators, AMD which makes CPUs and [67:15] GPUs, Qualcomm um which makes modems so [67:19] like networking devices as well as [67:20] mobile devices and then MediaTek which [67:23] makes also many different mobile system [67:25] on chips or many different mobile chips. [67:27] Then you have in-house silicon which is [67:30] um used in its own products. So like [67:32] Apple makes its own chips for its own [67:34] devices. The same it goes for Google [67:36] with TPU, AWS with graviton and tranium [67:39] and Microsoft with its own um AI [67:41] accelerators. Although the success of [67:43] those is varying, I'm not actually sure [67:45] on how well those are performing. And [67:46] then you have custom silicon which is [67:48] co-designed for a specific customer. In [67:50] this case, we have Broadcom which makes [67:52] custom AI and networking actually for [67:53] for Google even though Google has now [67:55] started to make its own. So [67:56] interestingly the Google TPU8 which is [68:00] the latest version is made half by [68:03] Broadcom and half by Google. Uh the [68:06] reason for this is that previously [68:07] Google was making the TPUs through [68:09] Broadcom exclusively but since they [68:10] wanted to reduce their independence on [68:12] Broadcom they made some of it in-house [68:15] although this this seems to have [68:16] backfired actually if you look at the [68:18] specifics which I would invite you to [68:20] do. And then you have Marll which makes [68:22] custom AI and also importantly like [68:24] interconnect and networking. So here you [68:27] have a few of the main players that [68:29] contract to the foundaries for wafer [68:31] fabrication like TSMC and Samsung. And [68:33] soon you'll have SpaceX on this list as [68:35] well making their terapab and they are [68:37] for example partnering both with Intel [68:39] and Samsung if I'm not mistaken in order [68:41] to ramp up production on their terapab [68:44] somewhere in the US desert. So that's [68:48] fabulous for you. Now, let's jump into [68:49] Foundaries, which you've already [68:50] actually presented quite well, but we're [68:52] going to go into even more depth because [68:54] most leading edge fabas designs are [68:55] manufactured by TSMC and you really need [68:58] to know a lot about TSMC to understand [69:00] the dynamics of the industry and how [69:02] important they are to the semiconductor [69:04] ecosystem. So here in terms of [69:07] foundaries right you have TSMC, Samsung, [69:09] Intel and then a few others which uh [69:11] we'll skip over for now but each one is [69:14] an interesting case study and these are [69:15] the guys that are actually manufacturing [69:18] and you would also another term that you [69:20] can refer to call these is a pure play [69:22] foundry which is say like a pure play [69:24] would be focused entirely on one thing [69:26] and in this case TFCMC is focused [69:29] entirely on producing chips. It does not [69:30] make its own chips to sell. It's a pure [69:32] play foundry and the advantage that TSMC [69:36] has over its competitors just um to [69:38] briefly state it is that they have [69:40] advanced node scale. So at the most [69:42] latest nodes they have the most volume. [69:44] They can learn from this volume in order [69:46] to improve their yields. And they have a [69:48] really robust co-qualified design [69:50] ecosystem which just means that they [69:52] have a list of vetted partners for EDA [69:55] and other processes in terms of [69:57] designing chips which are proven and [70:01] tested to be compatible with the TSMC uh [70:04] the TSMC fabrication process. Whereas [70:06] perhaps with other foundaries that are [70:07] on this list, you might have to like [70:10] piece a bunch of different um tools [70:12] together like Lego in order to make [70:14] something working with TSMC there is a [70:17] qualified uh design ecosystem that is [70:19] used in terms of ensuring that uh chips [70:23] are designed with the least likelihood [70:25] of running into catastrophic issues in [70:28] terms of like fabrication process. So [70:31] quickly the history of TSMC dates back [70:34] to 1987 when Taiwan backed this pure [70:37] play foundry which was one of the first [70:39] of its kind if not the first. The the [70:41] most interesting statistic about TSMC is [70:44] the fact that its CEO Morris Chang who [70:46] is a legend in Taiwan was 56 when he [70:48] founded TSMC. So nowhere near the [70:51] 18-year-old Stanford dropout that we're [70:53] seeing nowadays. And um what what [70:55] experience did he have? Well, he had a [70:56] lot. So he was at Texas Instruments for [70:59] 25 years and ran the global chip chip [71:03] business there. He was actually passed [71:05] over for CEO and then after was [71:07] recruited for uh Taiwan by Taiwan's [71:10] government to lead a chip effort there. [71:13] And interestingly uh the started the [71:15] starting capital came 48.3% from the [71:18] state so Taiwan itself. Um then 27 27.5% [71:23] from Phillips. So interesting [71:25] interestingly Philips has both seated [71:27] ASML and TSMC which are arguably two of [71:30] the most important companies in the [71:32] semiconductor semiconductor industry. [71:34] And even more compelling to know is that [71:37] the US chip makers actually declined to [71:39] invest in um in TSMC originally and when [71:44] they first started in terms of the [71:45] process tech it was licensed and also [71:47] was two to three generations behind the [71:50] leading fab at the time which is Intel. [71:52] So they were already playing a catch-up [71:54] game when they started the company. [71:57] And now the GDP of Taiwan is actually [72:01] less than the market cap of of TSMC. I [72:03] think it's double the market cap. So the [72:05] the market cap of TSMC is like double [72:06] the the GDP of the country which is [72:08] insane statistic. Uh it's such an [72:10] important company in that country and in [72:13] the world in fact. So as we know TSMC [72:15] makes chips and one thing that's really [72:18] important in the chip industry that is [72:20] literally like the difference between [72:22] life and death is yield and I just want [72:26] to introduce the concept of yield [72:27] through an intuitive example which um [72:30] talks about the size of dyes. So the [72:34] short of the stick here is that at the [72:36] same defect density larger dyes lose [72:39] more yield. And what this means is that [72:42] let's say that you have 1 2 3 4 5 six [72:45] defects at the same density across two [72:47] different uh chip designs. Well, one [72:50] defect can kill one entire die. And if [72:53] you have larger dyes, then these defects [72:56] can do more damage. And this is one [72:58] reason why actually the cerebrus wafer [73:01] scale engine, which is the size of an [73:02] entire d an entire wafer, right? You [73:04] actually don't even cut up or dice the [73:06] dyes after you uh pattern these uh [73:09] cerebrous wafers. you literally just [73:10] keep it intact. Um well, they're [73:13] susceptible to poor yield, but because [73:15] of this, they actually have redundancy [73:16] in the wafers that are made by Streus, [73:18] which is to say that they have ways for [73:20] um the chip to like essentially route [73:23] around dead nodes and just ignore them [73:26] if they fail. Because if not, an a [73:28] single imperfection on this 30 cm die [73:31] would mean that you have to throw away [73:32] the entire chip. And this is why as [73:34] we'll discuss later on the fabs need to [73:36] be so clean because a spare particle of [73:38] dust or something that lands on a die [73:41] can ruin the entire yield. So if we want [73:44] to look at this from a first principles [73:47] uh perspective we have the pson model [73:49] which is the following. So the ratio of [73:52] working dies to total eyes which is your [73:54] yield is equal to the exponential of the [73:56] negative area times the killer defects [73:58] per unit area. So this means is that um [74:01] if you have a larger die, if you [74:03] increase the area or if you have more [74:04] defects per unit area, then you'll have [74:07] exponentially fewer working dies or [74:10] exponentially less yield. Um this model [74:14] does assume that defects land randomly [74:16] independently, which isn't the case. [74:18] like defects tend to like land in [74:20] clusters or around the same area, which [74:22] would actually make the yield better [74:23] because if you have a bunch of defects [74:25] in a specific area that's concentrated, [74:27] then only that die will be concerned. [74:30] Whereas if they're randomly dispersed, [74:32] then you'll have like the maximum [74:33] damage. But um here we have once again Y [74:35] as the probability that a die contains [74:37] zero killer defects. And in reality, [74:40] FABS will probably use a clusterbased [74:43] defect model uh such as a negative [74:45] binomial distribution, which we're not [74:47] going to discuss because it's not really [74:48] necessary. But um with this model in [74:50] hand, the next slide shows why more [74:52] defect data can create a flywheel for [74:56] improving yield. So let's look at this [74:58] right now. Um essentially for a fab that [75:02] makes semiconductors, scale improves [75:04] yield and funds both the next node. So [75:06] let's look at this little flywheel here. [75:08] You can start anywhere. Let's start at [75:10] at um more defect data. So if you have [75:12] more defect data, which is to say like [75:14] more information on what's causing [75:15] defects, you can increase your yield. [75:17] And this is just done through pure [75:19] science. TSMC for example has many PhDs [75:22] that work on this specific problem day [75:24] in and day out. And then if you can make [75:27] your higher if you can make uh yield [75:30] higher then you can get more designs [75:33] created from your customers which gives [75:36] you revenue that you can reinvest into [75:37] more capacity and then from this [75:39] capacity you can increase your volume [75:41] and then from this increased volume you [75:43] get more defect data. So you can get the [75:45] uh the image here. Um this entire cycle [75:49] is very capital intensive. So it [75:51] requires a lot of investment and I I [75:54] mentioned that um we have like in the [75:56] 2020s about $20 billion in capex [75:59] required per year to sustain this [76:01] advanced technology and in fact for TSMC [76:04] last year they're at 40.9 billion and [76:06] this year they're somewhere between 52 [76:07] and $56 billion of capex on their [76:09] technology which is insane even more so [76:12] if you consider the daily cost which is [76:14] $150 million. Um, this is also true [76:17] because as you may or may not know, [76:19] they're building fabs in the US, in [76:20] Germany, as well as in Japan. So, [76:22] they're really um de-risking and [76:25] building out in more countries. But it's [76:28] worth noting, and we'll re-emphasize [76:30] that the most advanced nodes remain in [76:31] Taiwan. And one of the most amazing [76:33] things about TSM TSMC's history is that [76:37] since somewhere in the 2010s, Apple has [76:40] exclusively led TSMC's advanced node [76:43] ramps. And what does an advanced node [76:44] ramp? means it means that when TSMC [76:47] introduces a new node which has improved [76:50] performance, power and area, it was [76:52] always Apple that was leading this [76:54] production in terms of they were the [76:55] ones that were getting these chips [76:56] built. Um, now this is actually changing [76:59] which is kind of unfortunate for Apple [77:00] just because they're kind of being [77:01] pushed out by they're being essentially [77:03] priced out of this market by the um AI [77:07] accelerator industry. But this is still [77:09] the case up to the 2nmter process and [77:13] essentially 17% of the fiscal year 2025 [77:16] revenue for TSMC came from Apple and [77:18] TSMC has been the exclusive foundry [77:20] supplier since the mid2010s for them. [77:22] Um, but if you now look, it's tilting to [77:25] the favor of Nvidia because 90% of the [77:28] revenue has come in has came from them, [77:30] which is their largest customer. But [77:32] what's worth noting is that Apple has [77:33] played a really important role in TSMC's [77:35] success because every year they would [77:38] commit enough iPhone volume to make [77:40] these new node ramps economically viable [77:42] since it's such an expensive investment [77:44] in terms of research and improvement [77:46] yields, etc. uh there needs to be some [77:48] guaranteed amount of volume that they [77:49] can produce on these nodes so that all [77:51] of a sudden their customers don't just [77:53] go away and now you have this new node [77:55] you spend a bunch of money on and [77:56] nothing to do to build CPUs with it or [77:59] any type of chip. Importantly, right, [78:00] when you had Apple building these chips, [78:02] it would give TSMC early defect data, [78:05] helped yield mature, which is to say [78:07] increase yields and spread these costs [78:10] across longer production runs to [78:12] amortize the expensive nature of [78:15] establishing a new process and then once [78:17] it stabilized, TSMC could offer that [78:20] process node to more customers, which is [78:22] the trend that has happened. And [78:23] essentially you would have Apple at the [78:24] bleeding edge of TSMC process node [78:26] technology and the few other customers [78:29] trailing behind them in like the the [78:31] previous generation. So I also mentioned [78:35] that the gate allaround [78:37] uh field effect transformer was actually [78:39] first pioneered by Samsung and in fact [78:42] has not even been put into production [78:44] yet by TSMC. And this demonstrates that [78:47] foundry leadership which is owned [78:49] currently by TSMC requires more than [78:51] just being first because we have a [78:53] four-year difference already on the gate [78:54] all around. And Samsung is behind TSMC [78:56] by all accounts. And if we actually look [78:59] at GA plus backside power, this has been [79:02] done in 2025 already by Intel in their [79:04] 18A process. And back power is [79:06] essentially feeding power to the [79:07] transistor from the backside, which just [79:10] allows you to have higher power density [79:12] and feed in power more effectively. [79:14] Despite these two differences, TSMC has [79:17] led production by qualifying the whole [79:19] platform, not just one feature. And now [79:21] let's actually talk about this whole [79:22] platform in detail because that's what [79:24] it determines if a company can actually [79:25] ramp up to high volume production, which [79:27] is where the money is. So a dependable [79:30] foundry needs all five of the following. [79:32] It needs the process technology, which [79:34] you can think of as the transistor [79:35] structure, such as these different types [79:37] of transistor [79:40] layouts like a gated allaround or [79:41] backside power. It also needs the [79:43] qualified process development kit and [79:46] intellectual property which is to say um [79:48] the process development kit is the set [79:50] of terms and protocols which define how [79:54] chips are produced for a specific [79:56] platform. It also needs reliability and [79:59] the yield needs to be high enough and [80:01] the capacity needs to be enough to [80:03] actually justify all of the investment [80:05] needed to come up with a new process [80:06] node. And what this gives you is a [80:08] dependable foundry platform. That is why [80:11] being first to announce a feature can [80:12] differ from sustained production [80:14] leadership. And even more importantly, [80:17] before customers commit to high volume [80:19] product nodes, uh they they look for all [80:22] five of these being mature so that they [80:24] can depend on this production actually [80:28] leading to fruition. Because the last [80:30] thing that a company that is contracting [80:33] to one of these fabs wants is they have [80:36] invested a lot of time and money into [80:38] getting a chip working with them. And [80:39] then it turns out that in production [80:41] they can't even produce the chip [80:43] effectively andomi and economically. [80:47] So specifically for the latest process [80:49] in in TSMC currently N2 is the one that [80:54] is shipping right now and A16 is the one [80:57] which will add backside power. So this [80:59] is going to be in the second half of [81:00] 2026. And I did state that the gate [81:04] allaround has not been put into [81:05] production yet by TSMC but I suppose I'm [81:08] mistaken. So I apologize. HVM which [81:11] stands for high volume manufacturing [81:13] seems to have been achieved last quarter [81:15] of 2025 for the uh gate all-around [81:18] transistor. So very good to note that. [81:21] And then the A14 which is the note [81:24] process node which will succeed A16 is [81:26] going to be their second generation GA [81:28] in 2028. Interestingly, TSMC plans no [81:32] high NA EUV in production through 2029 [81:36] to extend the use of its low NAEUV [81:40] tools. And essentially all you need to [81:42] know here is that um these ASML [81:45] extreme ultraviolet lithography tools, [81:48] the latest and most expensive ones are [81:50] high NA which is the most precise and [81:54] companies like Intel have already bought [81:56] these as well as Samsung and SKH if I'm [81:59] not mistaken. But um TSMC has decided [82:01] that well essentially they can make use [82:04] of the current machines until 2029 to [82:07] once again have this trend where they're [82:09] not going to be the first adopters for [82:11] every new technology but they'll make [82:13] sure that their entire platform is the [82:16] best for leadership and uh maintaining [82:18] their edge. Okay. And now let's talk [82:22] about some reported wafer prices that um [82:25] are not confirmed but um these are [82:28] numbers that are circulated in the [82:30] industry because TSMC never publishes [82:32] figures. And one thing worth noting [82:34] first of all is that the prices do rise [82:36] with each new node. So I'm not going to [82:38] just speak out the numbers here but you [82:40] can see this increase in price. And of [82:43] course a wafer quote is not a finished [82:44] chip cost. the uh die area, usable dyes, [82:48] yield, memory, and packaging, determine [82:49] the cost per accelerator. Like this is [82:51] this is just the sorry this is just the [82:53] logic on the wafer. You're not even [82:55] accounting for the HBM which you need to [82:57] add on top of that or not on top of that [82:59] but beside it. And in fact, HBM is one [83:01] of the most expensive components of the [83:03] process of making an AI accelerator. And [83:06] that brings us to our second choke [83:08] point, which is leading edge foundry [83:11] capacity. In fact, Taiwan Semiconductor [83:15] Manufacturing Corporation controls an [83:18] estimated 90% of sub7 nanometer class [83:23] output for CPU and other semiconductor [83:28] logic which is just mindboggling. Uh 90% [83:31] of the most advanced process nodes are [83:33] owned by TSMC. Intel and Samsung also [83:36] make leading edge chips but much of [83:38] their capacity serves for their own [83:40] products. Um and the exact shares also [83:42] depend on whether an analyst counts [83:43] internal production. Um yet merchant [83:46] customers have few alternatives at the [83:47] leading edge. So when we talk about [83:49] merchant logic, it's the the [83:52] semiconductors that are not being made [83:53] for internal capacity or for their own [83:56] uh capacity but rather for other f uh [83:59] fab companies such as Nvidia. [84:03] So another thing also that we'll talk [84:05] about is in terms of just the foundry [84:07] TSMC is 11 times larger than Samsung [84:10] Foundry. So Samsung Foundry is [84:11] specifically the fab division of [84:13] Samsung. And if we look at some of the [84:15] financials here, we have $122 billion uh [84:18] which is an a 33 36% increase for fiscal [84:22] year 2025. The margins are still [84:24] relatively high, 67.7%. [84:27] Of course, not as high as Nvidia, but [84:29] given that these guys are dealing in [84:30] actual silicon, it's still impressive. [84:33] And then the global foundry share in Q1 [84:35] of 2026 is 72.3%. [84:38] And Samsung held 6.5% in the same Q126% [84:42] estimate uh Q1 2026 estimate. So this is [84:45] where the uh the 90% helps a lot, right? [84:48] So of course 90% of sub7 nanometer and [84:51] then if you look at the entire foundry [84:53] share it's of course less because not [84:55] all process nodes there's many material [84:57] nodes like if you think of auto chips [84:59] manufacturing those are all much uh less [85:02] advanced because you don't really need [85:03] the latest and greatest to make a key [85:06] fob switch for example [85:12] and so since this is 72% right replacing [85:15] this capability would require new fabs [85:17] scarce equipment a whole design [85:18] ecosystem and accumulated yield learning [85:21] which is really just tacet knowledge. So [85:24] no single metric can really capture to [85:26] what extent TSMC is embedded and [85:29] important for the global foundry [85:31] industry. And because they're so [85:34] embedded um there's efforts to [85:35] diversify. So because they're so [85:38] concentrated, they've now gone, for [85:40] example, in Arizona, which has the most [85:43] advanced overseas process node for TSMC, [85:46] the N4, which is actually at high volume [85:49] manufacturing according to them. And [85:51] then they also have Dresden in Germany, [85:52] which is for auto and industrial uh [85:54] capacity, and then one in Japan as well, [85:56] which is a slightly uh [86:00] less advanced process. So 12 to 28 [86:02] nanometers. But then if you look at the [86:04] next nodes and the current process node, [86:05] the most advanced are all in Taiwan. [86:07] Here's a closeup of uh the the island [86:10] and uh where specifically each of the [86:13] nodes that are being advanced are being [86:16] made. So this is the state of affairs [86:19] for the concentration of the leading [86:21] edge. And if we look at the previous [86:24] concentration which was Intel, uh we see [86:26] a sad story but let's still talk about [86:28] it since it's very instrumental to the [86:30] current state of affairs in the silicon [86:32] industry. So Intel of course one of the [86:35] other foundaries lost the process lead. [86:37] Uh this occurred somewhere around 10 [86:40] years ago when they had many delays for [86:43] the 10 nanometer process and they also [86:46] missed a few opportunities such as [86:47] mobile and AI. uh and now we'll see to [86:50] what extent they can recover um with the [86:52] the newest efforts they have to uh to re [86:56] reimpose themselves as the industry [86:58] leaders. So let's look at the history of [87:00] Intel. 1968 was founded by Noise Moore [87:04] if you've heard of Morris law that's him [87:06] and then Andy Grove who was the guy who [87:08] is famous for um being very paranoid or [87:10] instilling this culture of like paranoia [87:12] essentially saying only the paranoid [87:14] only the paranoid survive. And then from [87:16] 1970 to 1985 that was their DRAM uh [87:19] leadership until 1985 when since DRM is [87:22] a commodity it seemed there was a crash [87:24] and they exited the DAM market [87:26] completely. Um and then in 1981 [87:30] its processor was selected for the IBM [87:32] PC and it dominated the Intel um system [87:36] for three decades after that and at [87:38] actually the peak 99% of data center [87:41] CPUs were Intel and then um from 2007 to [87:46] 2016 they would alternate between a new [87:48] process and architecture on alternating [87:50] years. The most insane statistics of all [87:53] though is that the market cap of Intel [87:55] reached $500 billion in August 2000 and [87:58] did not surpass it for another 26 years. [88:00] So sometime this year they passed $500 [88:02] billion. But if you invested in August [88:04] 2000, then you would have had to wait 26 [88:06] years to get your investment back to [88:08] what it was worth initially. So it's [88:10] quite impressive to what extent there [88:11] was a bubble that time. But um let's [88:14] talk about kind of where they went [88:15] wrong. So [88:18] the 10 nanometer process node was where [88:20] they had many delays and one of the [88:23] reasons was is that they tried to go for [88:25] a 2.7x density bet. Um and this is [88:30] without extreme ultraviolet lithography [88:33] which is once again the more precise [88:35] patterning lithography tool which would [88:37] allow them to more easily reach the [88:39] skull. Even without that they wanted to [88:41] get this much density which is outside [88:43] of the 1.5 to 2x range which is which [88:46] would be more typical. And in order to [88:48] do this uh they essentially had to use [88:50] something called multi multiatterning. [88:52] So let me just explain this simply. You [88:55] have these lithography machines that are [88:58] shooting lasers at silicon in order to [89:00] make a pattern. And the more advanced it [89:03] is the more precise you can have these [89:05] patterns. And let's just say that you [89:07] don't have the most precise machine. So [89:09] you do instead is you kind of have [89:12] multiple designs and you go one layer to [89:14] do one design and then you kind of like [89:16] shift it and then you do another layer [89:19] uh with another design. So you can kind [89:21] of artificially have closer pitches, [89:23] closer transistor distances. But the [89:26] problem here is that um this means that [89:28] the yield will will sink because you'll [89:31] be you'll be bound essentially to more [89:33] more and more problems with u the the [89:36] chip not being properly produced since [89:38] you have more sophisticated [89:39] multiatterning as opposed to only one [89:41] patterning layer. And so if we look at [89:43] TM7C who in 2018 shipped their N7 [89:46] process and N7 plus with EV in 2019 [89:49] followed by N5 in 2020 on July 2420 [89:53] Intel announced another 7 nanometer [89:55] delay and on that day for example their [89:57] shares fell 16%. So you can see that [90:00] this is really the the main period where [90:01] Intel was dropping the ball and TSMC [90:04] became the clear leader. So not only [90:08] that but three markets moved away from [90:10] the x86 architecture. So first of all [90:13] there was the original iPhone chip in [90:16] 2007 which Intel passed on bidding it [90:19] and the volume actually was 100 times [90:21] greater than what was forecasted. Then [90:23] we have in 2020 when Apple leave Intel [90:26] for ARM as well as for example AWS [90:29] doing for more than 50% of their new CPU [90:32] capacity on ARM as well and AWS is a is [90:35] the largest uh data center provider in [90:37] the world. So this is not uh good news [90:39] for them either. And then of course if [90:41] you just look at AI Nvidia data center [90:43] revenue is 75.2 billion in 2026 whereas [90:46] Intel's is just 13.6 across their entire [90:50] uh across their entire company. So they [90:52] also missed out on AI unfortunately and [90:55] this all shifted demand away from Intel [90:58] to a different architecture or supplier. [91:01] So it was not looking good and in fact [91:05] 2024 was Intel's first annual loss since [91:07] 1986 with a negative 18.8 $20 billion [91:10] net loss, a 26% uh share decline, and [91:14] actually dividend was suspended in [91:16] reaction to this 1,500 layoffs, and this [91:19] was the N2024 to N2025 employee count. [91:22] So, large workforce cuts and repeated [91:24] leadership changes showed that investors [91:26] no longer view the problem as a normal [91:27] semiconductor downturn and made uh more [91:30] decisive action. With all of those [91:32] negatives, we have the 18A, which is [91:35] Intel's manufacturing recovery plan. So [91:38] they have Fab 52 in Chandler, Arizona [91:40] which is going to be constructing these [91:43] and they have their first gate [91:44] all-around transistor called the ribbon [91:46] field effect transformer as well as [91:48] power via which is the backside power [91:49] introduced ahead of TSMC interestingly [91:52] which is producing chips such as for [91:53] example the clear water forest which is [91:55] a 288 core zeon chip and then their [91:58] panther lake which is a laptop processor [92:00] which has already actually entered into [92:01] production and so in 2025 volume [92:03] production began but there is no yield [92:06] that has been disclosed. [92:08] And if in terms of external foundry [92:10] revenue, it's only $293 million compared [92:13] to the many billions for TSMC. This is [92:15] once again because Intel is only mainly [92:17] making its own chips instead of selling [92:19] to others. In fact, um most of the [92:21] external foundry is to a company called [92:23] Altera who used to be a part of Intel [92:25] but was deconolidated. It's like split [92:27] back out. Um, so really if they're [92:30] considered external is uh up to [92:31] interpretation, but um this number shows [92:33] that the vast majority of revenue is [92:36] still coming from Intel making its own [92:37] chips and then selling them. Um, and [92:39] since 2023, there has been more than $35 [92:41] billion in operating losses on their [92:44] foundaries. So you can see that they're [92:46] really operating on a lifeline here. Um, [92:48] as we'll see in the next slide, they're [92:49] getting a lot of support from the [92:50] government because of course it's the [92:51] only American pure play foundry and the [92:54] American government wants to probably [92:56] see them succeed. So likely it will not [92:59] occur that Intel like goes bankrupt or [93:01] something. And in fact, it seems that [93:02] they may or may not be turning around uh [93:05] to two brighter days. But for now, it's [93:08] still to be seen if Intel can really get [93:12] back into the position it once was. Um [93:15] in fact if you look at the Intel 14A [93:18] process which is accessor successor to [93:20] 188 it uses the high NEV which is once [93:23] again the most expensive lithography [93:25] machine that currently exists that is [93:27] made by ASML and the investments are [93:30] quite impressive. So $9 billion from the [93:33] US government 5 billion from Nvidia and [93:35] 2 billion uh from SoftBank and this was [93:38] all for equity. In fact this was last [93:40] year almost exactly a year ago. So this [93:44] is all the capital which is very good [93:46] news for Intel uh which can fund the [93:48] development but it cannot create [93:49] customers because actually there has not [93:52] been or as of my knowledge there's not [93:54] been an external anchor customer to [93:57] essentially substantiate all of this [93:59] investment. So they're going to need to [94:01] find a supplier to they're going to need [94:03] to find a customer to supply these new [94:06] chips to for volume production. Um so [94:09] this is another challenge that Intel is [94:12] facing. They have a lot of capital to [94:14] expand to their next process node, but [94:16] um they need to have customers to sell [94:18] to. So if you look at revenue just on a [94:21] quarter 2 basis from 2026, it was $16.1 [94:24] billion. And then the gross margin was [94:27] pretty low, 41.8% if you compare it to [94:29] Nvidia, almost half. And then um this PC [94:32] CPU shares, the majority of Intel, once [94:35] again, they lost out both on mobile, [94:36] both on AI. So, it's still CPUs that [94:39] mainly brings in their uh their share of [94:42] um revenue, but once again, they're the [94:44] only US-owned leading edge logic [94:46] manufacturer. So, for this reason, uh [94:48] they still receive lots of support from [94:50] the domestic supply chain and ecosystem. [94:53] The government being one example. So, if [94:56] we take a step back and look at the [94:57] current frontier of foundaries, TSMC, [95:00] Samsung, and Intel now ship leading edge [95:02] logic at scale. Um there is however the [95:06] statebacked Japanese company Rapidus uh [95:09] which is here that will attempt to join [95:12] them in 2027 with their current strategy [95:15] which is to directly start production of [95:18] a 2nmter process node from nothing. So [95:21] if we look at a graph here of the [95:23] frontier [95:25] except TSMC and Intel, we have Samsung [95:29] which introduced their 3 nanometer gated [95:32] all around in 2022 had issues with yield [95:34] but was able to overcome them. We have [95:36] global foundaries which is actually a [95:39] well-known semiconductor manufacturer [95:40] which exited the frontier at the 7 [95:42] nanometer process. It was just too [95:44] complicated and expensive. They decided [95:45] to focus on previous generation process [95:48] nodes instead. And then Rapidus who [95:50] wants to literally just jump onto the [95:52] bandwagon at 2 nmters with their pilot. [95:54] So we'll see how that goes. And then [95:55] Smick, which is the Chinese foundry that [96:00] is actually making 7 nanometer chips [96:03] without any EUV. And this is done [96:05] through multiatterning. Here you have a [96:07] diagram of what multi pattern look like. [96:09] Essentially just using multiple [96:10] different masks when you make these [96:12] patterns on a chip in order to achieve a [96:14] higher resolution than is simply offered [96:16] by one simple pattern. And this is the [96:19] current state of affairs of the fabs [96:23] across the world. But the fabs depend on [96:26] a separate equipment industry in order [96:28] to create and fab their chips. So TSMC [96:32] runs the fabs and so do its competitors. [96:34] However, ASML, applied materials, lamb [96:37] research, ka, these are the people that [96:39] build the key equipment inside them. [96:42] ASML supplies ethography. Applied [96:44] materials and lamb research cover [96:45] deposition and etch which we'll discuss [96:46] in detail. and KI KLA supplies [96:49] inspection and process control. And to [96:51] explain precisely what KA does, they're [96:53] essentially testing whether or not the [96:54] chip that has been produced is [96:55] functioning correctly. And this is [96:57] important because TSMC doesn't want to [96:59] give chips to Nvidia that turn out to [97:01] not work. So now we're going to talk [97:04] about how deposition, lithography, etch, [97:06] and inspection build a chip. So before [97:10] we get into the more sophisticated [97:12] layers of the WFE, so wafer fabrication [97:16] equipment process, let's talk about the [97:17] wafer itself, like the silicon and a [97:19] mask set that enter the FAP. So the [97:21] wafer is very interesting. It's called [97:24] 119 pure silicon because this is the [97:27] purity of the silicon that enters the [97:30] TSMC factory. So these discs are 300 mm [97:36] circular and uh this means like 1 foot [97:39] by 1 foot in imperial as I said before [97:41] and they're also made in silicon ingots. [97:45] So essentially it's a silicon ingot that [97:47] is 1.5 m in height and then you slice it [97:50] in uh with a diamond saw in order to [97:52] arrive at these these uh these silicon [97:54] semiconductor discs and they're [97:57] approximately $100 to $200 per blank [97:59] which is to say a piece of semiconductor [98:02] silicon that has not been etched. Um [98:04] some of the main manufacturers are I [98:06] think these are the two main ones both [98:07] Japanese are Shinetsu and Sumo. [98:11] And as I've mentioned multiple times so [98:13] far in this video, you use masks in [98:16] order to etch patterns into the silicon. [98:21] And these mask patterns are 5 to $15 [98:26] million per design because for a single [98:28] chip, you'll need between 80 and 100 [98:31] different masks. And it's of course [98:33] process dependent. So for example, the [98:36] mask that's required for the most fine [98:39] details that requires extreme [98:41] ultraviolet lithography will be more [98:43] expensive than some mask that is used [98:46] instead with deep ultraviolet [98:48] lithography which is a less [98:50] sophisticated form of lithography. So if [98:52] we combine these together, you get [98:53] approximately 80 to 100 different masks, [98:56] 80 to 100 different templates [98:57] essentially, which you use to etch onto [99:00] this 99 [99:02] uh 11 9 uh silicon. And even before the [99:07] fab, there's one thing I want to mention [99:08] which is the spruce pine mining district [99:10] in North Carolina which has among the [99:12] world's or perhaps the world's highest [99:14] purity quartz which is used to make the [99:16] quartz crucibles uh that are actually [99:20] used in order to hold the silicon melt [99:23] while one one crystal is pulled. So [99:24] essentially how these silicon ingots are [99:27] made is you have a bunch of silicon that [99:30] is melted in this pure quartz crucible [99:33] that comes from North Carolina. And then [99:35] as you uh lift it out with some special [99:39] technique with essentially a piece of [99:41] the uh the crystal that has already been [99:44] formed as like the starter. Like if you [99:45] think of sourdough it's kind of a [99:46] similar principle. You have a starter [99:47] dough. Uh you essentially dip that into [99:49] the ingot and then you twist it and then [99:51] it twists out a silicon ingot. Um this [99:55] piece of crystal is then used once again [99:57] to slice into these wafers. Um and [99:59] interestingly the spruce pine pin [100:01] district is where all of the quartz [100:03] comes to make these crucibles. So for [100:05] example I think it was one or two years [100:06] ago there was a hurricane that hit the [100:08] east coast of the US and this quartz [100:10] became in very tight supply because the [100:13] mine was shut down until the hurricane [100:15] had subsided. So this is one of the key [100:18] lynch points of the silicon industry [100:20] that you can actually find where one [100:22] single spot in the world is supporting [100:24] an entire industry. So we said we have [100:27] these masks and we need to go through a [100:30] specific process in order to put the [100:33] pattern that's onto the mask onto the [100:35] actual semiconductor because essentially [100:38] you can think of semiconductors as [100:40] skyscrapers. um they can be up to 60 to [100:43] 100 layers and at the bottom you have [100:45] the transistors and then above the [100:47] transistors you have the wires that are [100:49] connecting them. So essentially you [100:50] build a semiconductor layer by layer and [100:53] in order to do this you need to deposit [100:55] film every single time uh which will [100:57] constitute the actual layer. So let's [101:00] now go through the entire process that [101:02] creates one layer of a semiconductor. [101:05] Starting off with deposit. So we can [101:08] think of every layer as being composed [101:11] of a material such as metal oxide. This [101:14] is one example of many different types [101:16] of metals that are used to create [101:19] transistors. And in particular um these [101:23] deposit stages are extremely precise. [101:25] They can be up to literally atom uh [101:28] precision thick thickness. So literally [101:30] like one layers of atoms. Um and then [101:32] this is placed uniformly across the [101:34] semiconductor. And then once you do [101:37] this, you have a coat of photoresist. So [101:40] as the name indicates, photoresist [101:42] essentially resists light. And this [101:45] layer is also applied uniformly across [101:47] the deposit. Essentially covering [101:49] deposit in a layer of film. Um why are [101:51] you doing this? It's essentially to have [101:54] a pattern that you can trace on. So um [101:58] the way that semiconductors are created [102:00] it, you don't actually directly cut the [102:03] deposited film. instead for reasons of [102:07] precision and others that are quite [102:09] complicated and even I don't know you [102:11] first put the deposited layer then you [102:13] put a layer of coating on top of it and [102:16] then you expose light it in in [102:19] particular extreme ultraviolet light [102:21] through extreme ultraviolet lithography [102:23] to that uh coating and then this will [102:25] somehow alter the coating and then [102:28] through a development phase um the the [102:31] part of the coat that was exposed to the [102:34] EUV V light will be removed and then now [102:37] you'll think of you have your layer of [102:38] deposited film that is unchanged with a [102:42] coated photoresist on top of it that has [102:45] now a pattern on it. And then once you [102:47] have this pattern revealed to the [102:48] develop stage, you'll etch it. And [102:50] there's um different chemical and [102:52] physical processes that are used in the [102:54] etch phase to essentially remove the [102:59] deposited film that is not protected by [103:02] the photoresist. So you carve it out and [103:05] there's also processes where like [103:08] instead of not removing the the the [103:10] protected part, it actually uh will [103:13] remove the protected part and keep the [103:15] other section uh preserved. So it kind [103:19] of can kind of be like an inverse [103:20] pattern there. Um and then here [103:23] you will strip and clean. So you can [103:25] think of etch as a phase where you're [103:27] removing lots of material. So you you [103:29] might have some residue. So you want to [103:32] remove the both the resist so the photo [103:35] resist as well as any residue remaining. [103:38] So I'm just going to quickly skip two [103:40] slides to kind of get an give an idea of [103:42] what we got going on here. So you have [103:43] the deposit. This is the yellow material [103:45] that will make up your transistors. It [103:46] could be a metal oxide. And then you put [103:48] the pattern which is done by putting the [103:50] photoresist and then exposing it and [103:52] then developing it and you get to the [103:54] pattern. And then the etchphase both [103:56] removes um this pattern or rather the [103:59] edge phase will remove this um this p [104:02] this piece of the deposit uh this piece [104:04] of the deposited film. And then in the [104:07] uh next one which is called strip/clean [104:10] you'll remove the photo resist you can [104:12] move on to the next layer. But strip [104:14] strip/ clean is actually not the last [104:16] step. [104:17] um implant does something called doping [104:20] and annealing. And if you'll allow me, [104:22] I'll also switch to the next slide to [104:24] explain that. [104:26] So doping controls which charge carrier [104:29] dominates. So let's say that you have a [104:31] pattern uh which is chosen by the mask. [104:34] In fact, the mask chooses a region and [104:36] chooses which region will not be uh will [104:39] not be etched. And then when you [104:41] implant, you will put some chemicals in [104:44] specific regions to get ptype or ntype [104:48] transistors. So, and as an example, [104:50] boron will give you a ptype region and [104:53] um phosphorus/ arshake will give you an [104:55] ntype region. And what is this stuff [104:57] going on? Well, P just stands for [104:58] positive and N for negative. And P type [105:01] is a type of transistor where there is a [105:04] general lack of electrons. So you can [105:06] think of as positively charged and then [105:07] end type as negatively charged and then [105:10] this keeps creates an electrical [105:12] potential. This is of course quite [105:15] simplified. So excuse me if this is not [105:18] 100% correct. Um and then species, [105:20] location, dose and depth help define a [105:22] transistor's electrical behavior. So [105:24] this is very important for the [105:25] electrical prov transformer. Um not a [105:28] transformer but a transistor. So this is [105:30] the implant stage. And then in the next [105:31] stage we have an anal which does a [105:33] repair and activate which involves a [105:34] short heat treatment to actually [105:36] activate uh these separate regions of [105:38] ptype and ntype transistors. So coming [105:41] back here now if I move my face down [105:44] this is the implant dope and anal stage [105:46] and then you have the polish stage which [105:48] makes sure that um the transistor is [105:51] atomically flat for the next layer since [105:54] we do this many many times. and then a [105:56] measure which can be split up into [105:58] inspect metrology essentially verifying [106:01] whether or not this entire one-step [106:04] process occurred correctly because you [106:06] can imagine that if you have a single [106:07] error then they will start to compound [106:10] and then your yield will go down. So you [106:13] definitely want to have a lot of [106:15] inspection going on. You would think [106:16] that inspection would be kind of a [106:17] trivial part of the semiconductor [106:19] process. But it turns out it's so [106:20] critical because of the sophistication [106:22] of the techniques used to make these [106:25] semiconductors means that if you're not [106:27] checking very often thath everything is [106:29] going well then you'll have a very poor [106:32] yield. So interestingly right the wafer [106:35] stays in the fab the whole time. It's [106:36] the tools materials and mass that change [106:38] around it. In fact, this is a relatively [106:41] well-known fact, but like some [106:42] semiconductors will move 100 km, which [106:45] is like 62 miles in a single TSMC [106:47] factory during its uh creation. So, [106:51] there's a lot of traveling going on. [106:52] It's like a student that is going [106:54] between its different classes for like [106:56] science, math, etc. once they hit middle [106:58] school/ high school, but even more uh [107:00] sophisticated than that. And so, in [107:02] summary, this is a map of recurring [107:03] operations. Not every single one of [107:06] these components will be required in [107:08] every single process step. This is [107:10] depending on are you building a [107:11] transistor layer? Is it a different type [107:13] of logic or are you simply uh creating [107:16] interconnect with copper dialectric. So [107:19] it's very sophisticated but um these are [107:21] the majority of the different stages [107:24] used to create a single layer which will [107:28] over time create a finished wafer. So [107:31] skipping past this slide which we [107:34] already said once again implantation is [107:37] a doping method used to create N and [107:41] Ptype transistors. There's also other [107:43] methods like three-dimensional devices [107:44] that may use plasma doping. So very [107:48] sophisticated methods that you can look [107:49] into in more detail. Here we have once [107:51] again the pattern decides where the [107:53] deposited film remains as uh the [107:57] overarching paradigm of how a single [108:00] pass works in terms of defining the [108:02] patterns on a semiconductor which occur [108:05] throughout the entire fabrication loop. [108:08] And if you're wondering why it takes on [108:12] the order of 3 to 4 months for one wafer [108:14] to come out of a fab, well, if we just [108:15] do the math, it's 1 to 1.5 days as an [108:19] average cycle time per mask level. Uh, [108:21] which each mask level this defines a [108:24] single pattern. And then the full mask [108:25] set, which as we mentioned is around 60 [108:28] to 100 if we come back to I believe it [108:31] was this slide here or 80 to 100 plus. [108:34] Uh if you just multiply these numbers [108:35] then you get 3 to 4 months as the [108:37] typical leading edge fab cycle. And it's [108:39] worth noting though that most elapse [108:41] time is queuing transport and rework [108:43] between tools, not the exposure itself. [108:45] It's not just like 3.4 months of getting [108:47] shot by lasers. Um you can even consider [108:50] the fact that like this is probably one [108:52] of the most sophisticated logistical [108:53] problems in the entire world. maybe even [108:56] more sophisticated than like global [108:57] shipping because of the complexity of a [109:01] a supply chain with this many moving [109:03] parts in a single factory. And this [109:05] leads to the 100 km travel time for [109:08] these chips. As just an example, it [109:10] could be more, it could be less. And [109:12] then inside the die when you actually [109:15] come out of the process, you can see [109:17] something like this. Of course, this is [109:19] once again quite crude, but importantly, [109:22] you have the transistor that occupies [109:23] the floor level. and then many layers of [109:26] wiring that rise above to connect the [109:27] different transistors. So this is a [109:29] cross-section of a transistor with [109:31] multi-layer inter interconnect with [109:33] advanced logic once again being [109:35] approximately 80 to 100 plus masks per [109:39] wafer and this doesn't mean that there's [109:42] 80 to 100 layers. So in the next two [109:45] slides we'll kind of discuss what the [109:47] masks are. So a mass level is one [109:49] patterning operation. A mask or reticle [109:53] is the physical master pattern loaded [109:56] into the lithography scanner and it it's [109:59] not one to one with physical layers as I [110:01] just said. So the three terms here we [110:04] need to know is the mass reticle is the [110:05] actual pattern. The mass level is one [110:07] distinct pattern of the set which is all [110:10] of the reticles needed for a single [110:12] design. And to iterate that it's not one [110:15] to one, right? If you have a a DUV [110:18] layer, you could have up to four mass [110:19] patterns for a single layer. Whereas EUV [110:22] because of its precision can collapse [110:24] several exposures into one. And the [110:27] thing is though that you still use DUV [110:29] for um many of the layers in a [110:32] transistor in a in a semiconductor. It's [110:34] not just exclusively EUV even in the [110:36] most advanced chips. It's a combination [110:38] of the two. Okay. And right on the topic [110:41] of contamination, [110:44] if we look at how clean these factories [110:46] need to be, um the cleanest TSMC fabs, [110:51] which are ISO1 rated, which is the [110:53] international standard, have less than [110:55] 10 particles per cubic meter, which is [110:58] just absolutely insane. I've heard the [111:00] statistic that in the most clean TSMC [111:02] fabs or plants, the entire air is [111:05] circulated every two seconds or [111:07] something insane like this. Um, they [111:09] also have other parts which are less [111:11] stringent where the ISO could be five, [111:13] which is 100,000 particles per cubic [111:15] meter. But even this is way cleaner than [111:17] like the room that I'm standing in right [111:19] now or any like average setting. Uh, and [111:22] why is this the case? It's because a [111:24] particle even about 100 nanometers wide [111:26] can bridge nearby wires causing a short [111:28] and kill an entire die. So the isoc [111:31] class is applied to this zones where you [111:35] want to avoid this from happening mean [111:37] meaning that the air literally is kind [111:39] of just empty and doesn't have any of [111:41] these particles apart from just like [111:43] pure atoms. And another way to picture [111:46] ISO1 is less than 10 particles per 1,000 [111:52] L. With that being said, let's now jump [111:54] into lithography. [111:56] So the installed N high uh system in [112:00] Intel weighs more than 150 metric tons. [112:03] And here's a diagram compared to a [112:04] person that is that's relatively to [112:07] scale. Um and Intel actually received [112:10] its first one in 43 freight containers [112:14] inside of the actual machine which is [112:18] the most sophisticated commercial [112:19] machine commercial machine ever built. [112:21] Of course, the large hajon collider in [112:23] Switzerland is the most sophisticated [112:25] machine ever built by humanity. But um [112:27] this is the most expensive commercial [112:29] machine ever built by humanity. And [112:31] inside you have a light source, vacuum [112:33] chambers, mirror uh mirrors, and [112:35] precision stages needed to keep a moving [112:37] wafer aligned at nanometer scale. [112:39] There's really good set of videos by [112:42] ASML itself on how uh these machines [112:44] work as well as Veritasium. So I highly [112:46] recommend watching those. But in any [112:48] case, we have a 14 mx 4 m machine that's [112:52] just a colossus and serves to [112:54] essentially perform the patterning stage [112:57] of the multi-step process of etching and [113:02] creating a semiconductor. So this [113:04] exposed step which is without a doubt [113:06] the most complex just because of the [113:08] machine that it requires. So let's look [113:11] at kind of how this works more [113:13] mechanistically. [113:15] The reticle pattern is here. And in [113:17] fact, the standard size is 132x 104 mm [113:20] for this specific machine, the ASML NXE [113:24] 3400 uh C and 3600D. These are also in [113:28] the range of like 400 million. So, this [113:31] is not something that is particularly uh [113:33] affordable. And then the reduction [113:35] actually occurs on this chip out of 4:1 [113:38] basis which shrinks down the exposure [113:40] field which is actually printed onto the [113:41] silicon to between to 33x 26 mm. And [113:45] then once again to go jump all the way [113:47] back to the beginning of this video [113:48] where we talked about the dyes on the [113:50] Nvidia GB300 Ultra. Uh because this [113:53] exposure field is limited in size. It's [113:55] a standard size and they wanted to build [113:57] a chip with a certain number of [113:58] transistors. They made two of these on [114:00] two dieseS and then connected them via [114:02] an interposer on uh the NVHBI system. So [114:06] when you're patterning a wafer, you [114:08] could have multiple patterns that are [114:10] being switched in and out because you [114:12] step essentially step across the wafer [114:13] and on a single wafer you can make many [114:15] different patterns and then you [114:16] essentially dice them. That's the word [114:17] that's used. Dice the pattern at the end [114:19] in order to get the single uh dyes which [114:23] each correspond to some type of silicon [114:26] design. [114:27] Here we're gonna take a image provided [114:30] by ASML. So thank you for their uh image [114:33] creation which shows the 13.5 nanometer [114:39] EUV extreme ultraviolet light that's [114:41] produced from tin plasma and then sent [114:45] into this optical column which is [114:46] composed of many different mirrors and [114:50] air and transmissive glass absorb EUV. [114:52] So the machine encloses the path in high [114:55] vacuum and uses multi-layer mirrors. So [114:57] there's no air in order to avoid um the [115:01] the light from being absorbed by [115:03] molecules. I believe there is some [115:05] hydrogen involved. So if you want to [115:06] like look once again at these videos, [115:08] they'll explain the exact process. But [115:10] um they also use mirrors instead of [115:11] lenses which was used in the more [115:13] primitive uh lithography [115:16] steps previously. The problem here is [115:18] that um if you use a lens then it will [115:21] absorb the UV light. And then these [115:24] mirrors are the most precise mirrors in [115:25] the entire world. They're made by Carl's [115:27] Ice. Uh and in fact Carl's ice is like [115:29] owned 49% by ASML. So it's like almost a [115:33] subsidiary of ASML. And these mirrors [115:36] are kind of like the one of the [115:37] bottlenecks on the ASML machines. If [115:39] they don't make these mirrors, then [115:40] these lithography machines will not do [115:43] anything. And to tell you how precise [115:46] they are, if one of these mirrors was [115:49] the size of Germany, why Germany? It's [115:51] just cuz Zeiss is made in Germany. So I [115:53] guess they chose that as a the country [115:54] as the example. If you made this mirror [115:56] as large as Germany, then the maximum [116:00] unevenness would be 0.1 mm. So imagine [116:04] the country of Germany being essentially [116:06] flat and the maximum elevation [116:08] difference being 0.1 mm. That's the [116:10] precision that we're talking about. And [116:11] once again, this is in order to reflect [116:13] the light as perfectly as possible. Cuz [116:15] if you look at like a standard mirror, [116:17] it looks flat, but at the microscopic [116:19] level, it's actually like a mountain [116:20] because of just um atom level [116:23] inaccuracies. But these mirrors [116:25] themselves are just so precise that you [116:27] get this crazy German sized mirror if [116:30] you made it with only 0.1 mm unevenness. [116:34] So we talked about Zeiss which is the [116:37] mirror which is used for collector and [116:39] optics but ASML also integrates a few [116:42] other components into its scanner rather [116:44] than building everything in inhouse. So [116:46] Trumpiff which is based in San Diego [116:48] makes the laser which is a 30 kow CO2 [116:51] laser that is used as a light source. [116:54] And then Simer is the company which [116:57] makes the tin droplet source. And [116:59] essentially once you pass the laser [117:01] through tin droplet, you can create this [117:04] extreme ultraviolet light. And then ASML [117:07] bundles this together with stages, [117:09] sensors, software, and a calibrated [117:11] vacuum in order to come out the other [117:13] side with this 4x4 m and 100 something [117:18] ton machine that is just the most [117:21] complex commercial [117:23] machine ever built. And so, as we [117:25] mentioned again, the leading edge fabs [117:27] like TSMC depend on ASML, which depends [117:29] on Carl Zeiss to make these mirrors. And [117:31] then if you go farther down into the [117:32] supply chain, you can probably find [117:34] which companies Carl Zeiss depends on to [117:37] make their mirrors. It's most likely a [117:40] another set of companies which are [117:42] probably somewhere else in the world. [117:44] And just demonstrate the extent to the [117:46] which this is a massively global supply [117:48] chain. And you can imagine that if [117:49] either ASML or Zeiss were running into [117:52] problems in terms of manufacturing or [117:55] procurement, then TSMC and others would [117:59] be at the mercy of their machines that [118:01] are currently under operation and would [118:03] have to pray that they continue to work [118:06] because if they stopped working, then [118:07] there would be no more machines coming [118:09] their way. All right, now let's look at [118:10] the financial outlook of ASML. They [118:12] expect 43 to4 billion of sales in 2026 [118:17] while expanding their EUV capacity. So [118:19] in quarter 2, they spent or well, they [118:22] sold $9.3 billion worth of lithography [118:25] machines principally with a 54% margin [118:29] and their outlook for the fiscal year is [118:31] between 43 and 45 like we said. And then [118:34] of course since these machines each cost [118:37] like in the order of hundreds of [118:38] millions of euros, they're actually not [118:40] making that many, right? So the low NEUV [118:42] machines which are the ones used by TSMC [118:45] and others there's only 65 being built [118:47] this year. Of course these may be [118:50] ramped. Um in fact management says in [118:52] 207 2027 the low any UV capacity is [118:56] nearly covered by orders. So this means [118:59] potentially that the order and capacity [119:01] will increase in ensuing years but even [119:04] so they need to sell only 65 to reach [119:07] these impressive revenue numbers. And so [119:10] I haven't explained yet what NA is with [119:12] high NA and low NA. It stands for [119:14] numerical aperture which is a unitless [119:17] measure of the light angles the mirrors [119:18] can collect in focus. So in fact 0.55 NA [119:24] is the numerical aperture of high NEV [119:27] whereas currently if you have a standard [119:30] uh generation NXC EV machine it's 0.33 [119:34] NA. And if we just convert this to the [119:37] resolution that you can get uh you can [119:39] have a 8 nm half pitch meaning an 8 [119:42] nanometer line we set an 8 nome space uh [119:45] so on a 16 nometer interval with these [119:47] new machines whereas the maximum [119:49] resolution for the current generation is [119:50] 13 nome okay and that's most of what [119:54] we're going to discuss on the terms of [119:55] lithography [119:57] let's also give a quick treatment to ND [119:59] NAND memory which is SSD and similar to [120:02] HBM it has also gone vertical [120:05] because we they want to increase the [120:07] density of the memory and in order to do [120:09] that you need to go in the three [120:10] dimension. So nan makers have moved from [120:13] planer cells like flat ones to vertical [120:15] stacks and the layer count has grew from [120:17] 24 in 2023 2013 sorry to thousand with [120:21] uh approaching road maps. However, today [120:23] it's more in the range of 200. Of course [120:26] each taller stack similar to HPM [120:27] requires more deposit films and a deeper [120:30] channel etched through them increasing [120:31] demand for deposition and etch [120:32] equipment. So this is a bull case for [120:35] deposit and edge companies and [120:37] furthermore uh it's a bullc case for [120:39] verification companies because the more [120:41] layers you melt the more you have to [120:42] verify that each layer is properly [120:46] coated, properly cleaned, properly [120:47] planed etc. Uh and therefore there seems [120:51] to be a demand which will only increase [120:54] for these wafer fabrication equipment [120:56] technologies. So who's actually making [120:58] this equipment? For example, applied [121:00] materials one of the best known is in [121:03] six of the eight wafer fab tool [121:05] categories. So here if you want to pause [121:06] the video and read which ones we have [121:08] like the big outlier here is lithography [121:10] which is owned by ASML and which applied [121:12] material is not participating in but [121:14] otherwise it's in many of these [121:16] industries. So in this case they can [121:19] capture spend across most process steps [121:21] even without owning um one of the most [121:24] expensive lithography and this is a [121:26] great company to expose to if you want [121:28] to just be involved in most of the WFE [121:32] uh industry and then if and then if you [121:35] want to have a complete coverage you [121:36] would just buy some stock in ASML and [121:38] then also track which we'll discuss but [121:40] that's Tokyo Electron. So coming back to [121:44] NAND um when we're doing this etch phase [121:48] there's wet and dry etch and dry etch is [121:50] the most precise version of it and it's [121:53] used specifically in these uh these [121:56] settings where you have to make hundreds [121:58] of layers because one channel must stay [122:01] straight through 100 layers essentially [122:02] to allow for information to pass from [122:05] the bottom to the top when you want to [122:07] transfer information between the [122:09] different layers. And once again this [122:11] means that a wafer needs billions of [122:13] these channels with consistent [122:14] dimensions because a miss can disable a [122:16] memory cell. Uh this is once again [122:18] necessity necessitating the need for for [122:21] very precise etch process and in fact [122:24] lamb research is one of the most [122:26] advanced providers of this etch. In fact [122:28] they can etch through a 3D NAND channel [122:31] through more than 100 layers in a single [122:33] pass reaching a depth about 50 times the [122:35] channel width. So extremely impressive. [122:38] So jumping back to Tokyo Electron, [122:40] they're the 90% owners of the share in [122:43] the track industry, which is essentially [122:45] the coding for the photo resist, which [122:47] then goes to exposure and then also the [122:49] developing, which um makes the exposed [122:52] photo resist go away in order to reveal [122:55] the pattern that was etched through the [122:57] lithography step. And then if you look [122:59] at another another important layer of [123:02] the uh process stack for making these [123:05] semiconductors, we have ASM which does [123:07] atomic layer deposition and uses [123:11] self-limiting reactions to deposit these [123:13] films around every side of a gate [123:16] all-around transistors channel. So we [123:18] remember the gate all around uh fine [123:21] field effect transistor requires you to [123:23] wrap around the entire surface and their [123:26] atomic deposition is using a specific [123:30] form of reaction to deposit all around [123:32] the gate and since we can see that for [123:35] example uh TSMC and all of the leading [123:38] fabs are going in the direction of gate [123:40] all-around transistors this is another [123:42] appealing industry and company to [123:44] specifically invest in and so the [123:46] overall trend in the past few years to [123:48] have vertical structures has meant that [123:52] these tool sales turn into decades of [123:55] service and a lot of reoccurring [123:58] revenue. So these taller nan stacks and [123:59] gate all around structures increase the [124:01] number of and difficulty of deposition [124:03] and etch operations. So toolmakers that [124:05] service their installed base for decades [124:07] have like in the case of lamb 36% [124:10] reoccurring revenue and they have [124:13] actually about 100,000 process chambers [124:16] in the field actually currently with a [124:18] 20 to 25 sur 20 to 25 year service life. [124:22] Um, so you can see that they're like [124:24] deploying these assets which then need [124:25] to be maintained and just they're [124:28] essentially reaping benefits over a long [124:30] term for these machines which must do a [124:34] very difficult task and therefore may or [124:36] may not need more often service than a [124:39] normal service [124:42] which as the 3D structures become taller [124:45] and taller will need more and more [124:47] service likely meaning that the [124:49] recurring revenue will only increase for [124:50] lamb. Okay. So, I've really been [124:52] emphasizing the need for measurement and [124:56] not only at the end but between critical [124:59] steps. So, one company that is doing [125:01] this is called KLA. So, KLA's tools [125:04] inspect wafers for defects and measure [125:06] dimensions after different process steps [125:08] for alignment. Their core inspection and [125:10] metrology tools measure rather than [125:13] depositing. And at nanometer scale, the [125:16] fab needs these measurements to detect a [125:18] bad process before it damages more [125:20] wafers and to remove a wafer out of the [125:23] production line earlier than just [125:26] waiting at the very end and realizing [125:28] that it had already been uh essentially [125:31] broken or not no good since like the [125:34] initial stages of the the manufacturing [125:36] step. This allows you to essentially cut [125:40] your losses much earlier when you have a [125:43] more robust and tighter feedback loop in [125:46] terms of measurement. So to illustrate [125:48] this point, if a process drifts at step [125:50] 400 of 10,00 without inline inspection, [125:53] the FAB discovers the process at the [125:54] final test after weeks of additional [125:55] work. Whereas at step 4001 with a [125:58] perstep uh process check, then your [126:01] cumulative losses will have been much [126:03] less than in the no inspection case. And [126:06] to give you an idea that this inspection [126:08] isn't just like trivial to do and you [126:11] can't just in instantly get into this [126:13] industry if you want. A killer defect is [126:16] 15 million times smaller than the wafer [126:18] itself. So a 20 nanometer defect can [126:20] ruin an entire die. And if you made this [126:24] a golf ball like the defect itself then [126:26] the wafer span would be 600 km in [126:28] length. just to give you another way of [126:31] realizing the the the magnitude or [126:34] rather the minuscule size of these [126:36] deepexs and um how how are they actually [126:38] finding these? It's through high [126:40] throughput optical inspection that uh [126:43] locates the targets and it uses like [126:45] electron beam mic microscopes to review [126:48] selected sites. And in terms of like how [126:50] long this takes cuz it definitely is not [126:52] a fast process. Well, the time depends [126:54] on the inspection recipe, sensitivity, [126:55] coverage and sampling plan. So there is [126:57] really no universal per wafer duration [126:59] but you can expect that this is one of [127:00] the reasons why you have wafers spending [127:02] 3 to four months inside of the fabs. So [127:05] if you look at like the fundamentals of [127:08] KLA its lead is unusually wide. They [127:11] have 56 to 58% of the market share which [127:14] is seven times greater than the nearest [127:16] rival. And this sums up to $13.58 [127:20] billion in revenue for fiscal year 2026 [127:23] and a gross margin of 61.3%. [127:26] So the thing is too these fabs like TSMC [127:29] they tune their inspection recipes to [127:31] each layer to each process window and to [127:33] the known defects. So switching vendors [127:35] to another uh metrology or inspection [127:37] partner does require new baselines and [127:40] recalation meaning that the embedded [127:42] process means uh the switching cost for [127:46] moving away from KLA is very good or [127:48] very high and therefore the market for [127:50] KA is very good. So shifting the [127:52] attention here to Japan which if you [127:54] recall used to actually lead the HBM and [127:58] DM industry now Japan's main moat is in [128:02] materials. Of course, they are trying to [128:04] make their own pure play foundry, but [128:06] that is yet to materialize. Instead, [128:09] they make the wafers themselves, right? [128:11] Shinu and Sumo as we've already [128:13] mentioned. Also, the advanced resist so [128:16] took electron and JSR and the EUV mask [128:19] blanks as well. So, these are the masks [128:21] that go into the EV machines before they [128:23] actually have the patterns on them. And [128:25] this is actually going to be the third [128:26] choke point in the video. Why would you [128:28] why would you ask? Well, it's because [128:30] whereas fabs buy major equipment at long [128:32] intervals, they consume the photoresist, [128:34] the gases, the slurries, and other [128:36] materials every single day that these [128:37] Japanese suppliers provide. And they [128:40] actually hold about half of the global [128:43] semiconductor materials market, even [128:45] though the Japan share of chip [128:47] manufacturing has fallen from its 1980s [128:49] peak. And because like these wafers, [128:52] resists and masks and other materials [128:53] are qualified essentially together into [128:56] a specific production process, changing [128:58] one can alter dimensions, defects, etc. [129:01] So essentially as soon as you have a [129:03] specific material combination for [129:05] process node, it's very unlikely that [129:07] will change which means that for these [129:09] Japanese material manufacturers, they [129:12] are able to have a relatively safe [129:15] ability to sell their materials once it [129:17] has been tested and the yield is [129:20] responding for a specific process note [129:22] at a fab. And to summarize, we have five [129:26] inputs which together create [129:28] semiconductors. So the wafer itself the [129:29] silicon substrate and then you have the [129:33] photoresist the coat which is also [129:35] Japanese. So these first two are [129:36] Japanese. Then you have the expose which [129:38] is like the actual reticle and the light [129:40] source. So these are instead mainly [129:44] coming from ASML. Then you have the [129:46] etch/clean which are mainly chemicals. [129:49] And then the polish [129:51] which is used in order to for example [129:53] flatten the layer of silicon before it [129:55] reaches the next stage. So these are the [129:57] five inputs that enter the fab loop from [129:59] the start and exit with a refined [130:03] semiconductor. So interestingly right [130:06] since these are materials the effect on [130:08] the supply chain when there's a shortage [130:09] is much more immediate since as we [130:11] mentioned they need to be consumed every [130:13] single day as opposed to like a machine [130:15] which will last for 20 years and if it [130:17] is not in supply well the effect may not [130:21] be seen until the machine that is [130:22] currently being used runs out. So for [130:24] example, Japan would supply photoresist [130:26] HF and polyomide to Korea. But in 2019, [130:29] it was quite interesting. There were [130:31] some disputes between the two countries [130:33] and some of it was actually related to [130:34] like World War II reparations uh which [130:37] caused Korea to or rather caused Japan [130:40] to ban exports to Korea and Korea had to [130:43] localize because the exports fell by [130:46] about 97%. And um this was quite a [130:50] significant fall and had many different [130:52] supply chain consequences. And then [130:54] unfortunately in the war in Ukraine [130:56] which is one of the main neon suppliers [130:59] this also meant that about half of the [131:00] supply was gone and then the spot price [131:03] went up 4x once both of the major [131:05] Ukrainian plants halted operations. You [131:08] can see here once again these caused [131:10] immediate disruption. And then when we [131:13] talk about the spruce mine which in 2024 [131:15] was um closed for 2 weeks by a hurricane [131:20] the the companies which required these [131:22] for their uh their crucibles in order to [131:24] make the silicon ingots started [131:26] stockpiling. So these are only some [131:28] examples of the different bottlenecks in [131:32] terms of materials. And there's another [131:33] one, for example, I know helium from [131:35] Qatar at some point was under threat of [131:38] being um under threat of of the Iran war [131:43] and that's led to certain speculative [131:46] spot price increases in helium. Okay, so [131:49] now we're going to do a quick interlude [131:50] and talk about the other 90%. What do I [131:52] mean about other 90%? Well, I'm talking [131:53] about the other semiconductors that [131:55] aren't just AI accelerators. So, let's [131:57] talk about analog and microcontrollers, [131:59] which use more mature nodes. So analog [132:03] semiconductors account for $90 billion [132:06] in annual revenue and then [132:09] microcontrollers 30 billion. These [132:11] products use notes introduced 15 to 40 [132:13] years ago and do not require EUV or [132:15] leading edge fab equipment. And a [132:18] controller for example that costs cents [132:20] can stop a $40,000 vehicle. This is what [132:22] we saw in 2021 when there were $7.7 [132:25] million fewer vehicles that could have [132:27] been produced that weren't, which led to [132:29] $210 billion in lost profit in the auto [132:32] industry and auto prices going up due to [132:36] a loss of access to inexpensive mature [132:39] node controllers during a 2021 shortage. [132:41] And I'd encourage you to look into the [132:43] history of this shortage in particular [132:45] because one thing that is interesting is [132:48] the fact that it seemed with hindsight [132:50] to be very predictable. However, none of [132:52] the automakers had prepared for it in [132:54] advance and were all left essentially [132:56] with their their mouths hanging open [132:58] when they realized that they could not [133:00] sell their cars because of a silly [133:02] controller that only cost a few cents [133:04] because it was not available. And so if [133:06] we talk about overall these devices [133:08] which belong in cars, factories, [133:10] appliances, etc., they combine many [133:12] specialized chips rather than relying on [133:13] one processor. And some names of [133:16] companies which manufacture these chips [133:18] are TI, Infion, ST Micro, NXP, [133:21] Renaissance and analog devices. So these [133:23] are industries which are more stable but [133:26] also would likely not benefit to the [133:28] extent of the AI accelerator companies [133:32] due to the uh the lack of AI integration [133:35] in these products. Okay. So now that the [133:37] interlude's gone, let's talk about [133:38] memory packaging and networking. So HBM [133:42] and packaging build the accelerator. But [133:44] um it's the fabric which is networking [133:47] that makes the system work. So just to [133:49] give a quick primer on um DM versus NAN [133:52] since we've already discussed the [133:53] difference between DAM and SRAMM. DM [133:56] stores each bit as a charge in a tiny [133:58] capacitor and refreshes on a cycle of [134:00] about 64 milliseconds and it's volatile [134:02] working memory because it needs some [134:04] electric charge to uh essentially [134:07] maintain state. If you turn off the [134:10] power then it will become empty. Whereas [134:11] NAND can trap charges for years without [134:13] power and um it gains density by [134:15] stacking hundreds of layers as opposed [134:17] to DM which we have discussed is [134:20] stackable but not to the extent of NAND. [134:22] And because of these differences in the [134:24] design, DRAM feeds active computation [134:26] while NAND provides persistent storage. [134:28] And why I mentioned NAND and DRAM in [134:32] particular is because a 2-year fab lag [134:35] can turn shortages into memory cycles. [134:39] So memory suppliers add capacity during [134:42] shortages, right? But a new fab takes [134:44] about 2 years and more than $15 billion [134:46] to build, which kind of adds this lag [134:48] period. And what happens is that several [134:50] projects can reach production together [134:51] and push prices down. So for example, [134:54] there's a shortage price rise, but then [134:56] in 2022 2023, prices roughly halfed and [134:59] inventories were actually 31 weeks, [135:01] which means that they had 31 weeks worth [135:02] of supply um because of this overbuild. [135:05] And then um after 2 years and these [135:09] repeated cycles, they had actually like [135:12] three companies left because the other [135:14] companies had been just beat by the fact [135:16] that uh the DM price had gone down so [135:18] much. These three companies being H uh [135:20] Micron, SK, Hinx and Samsung with 90% of [135:24] capacity and once the capacity arrive [135:26] and DRM is in short context the prices [135:30] contract and it goes up 93 to 98% in one [135:32] quarter. I think this was sometime in Q4 [135:34] 2025. Um and now we'll see if the prices [135:37] will fall, but up to now it's kind of [135:39] what people are calling a super cycle as [135:41] opposed to a regular memory cycle. And [135:44] um it seems that prices of memory will [135:46] only continue going up. And because DRAM [135:49] is such a commodity, it really does [135:52] favor the companies that keep on [135:53] investing and are able to invest even [135:55] during downturns. So Intel 1103 was the [136:00] first uh chip to introduce DM and this [136:02] this made the market in 1970. In the [136:05] 1980s, Japan had 90 75 to 80% of the [136:08] global DM share. But then there was a [136:10] crash in 1985 took out Intel also. I [136:13] believe Japanese uh companies lost their [136:15] their lion share. But then what happened [136:18] is that in 1992 Samsung became number [136:21] one which they held for 33 years. But in [136:23] 2025 SKH Highix became the leader for [136:26] DRM production between Q1 and Q3. [136:28] Interestingly Samsung retook it in Q4 [136:31] but if I'm not mistaken SKH Highix is [136:33] now leading again and one thing is SKHX [136:36] focuses exclusively on DM and HBM [136:38] whereas Samsung has many different [136:40] industries they make phones etc. So this [136:42] is one of the reasons why Skhonx has [136:44] been able to surpass uh Samsung at least [136:47] in DRM leadership. And once again the [136:50] worth the thing worth noting here is [136:51] that these companies are the ones who [136:53] kept investing even through downturns in [136:55] order to turn um the success of the [136:58] current day which is immense for these [137:01] companies. And if you think of why or [137:04] one of the reasons why memory became so [137:06] scarce in the past 20 years on servers, [137:09] compute capabilities grew by 60,000 [137:12] while the memory bandwidth feed grew [137:15] only 100x. And this means that you [137:18] essentially leave arithmetic units [137:20] waiting for weights and sitting idle, [137:23] meaning that you need just more and [137:25] better bandwidth memory. And this only [137:27] exacerbates the shortage of high [137:30] bandwidth memory. And in order to [137:33] alleviate this discrepancy between [137:37] compute increase and memory, there's a [137:39] few things that have been done. You've [137:40] already stacked HBM to have higher [137:42] memory density. But then also the memory [137:44] sits millimeters from compute in order [137:47] to minimize the distance between the GPU [137:49] die and the memory itself through this [137:52] uh essentially this collocation of [137:54] compute and memory. Then when it comes [137:58] to like the latest generations we have [137:59] HPM 3E which at the 12 stack version is [138:02] 36 and the 8 stack is 24 GB per stack. [138:06] Once again, 3 GB per layer. And this [138:09] memory uses a 1,024-bit or 1 kilobyte [138:13] bit interface, which moves about 1.2 TB [138:16] each second from one stack. That's just [138:19] in insane numbers. And what this means [138:21] is that um since you have eight of these [138:23] on the sides of the GB300 GPUs, then you [138:27] can actually multiply 1.2 by 8 and you [138:29] get approximately 8 terabytes per second [138:31] of memory transfer on a single GB300. So [138:35] of course 8 times 1.2 is 9.6 and this is [138:38] just because they conserably run the HPM [138:40] at 1 terabytes per second instead of [138:41] 1.2. So as I mentioned previously this [138:43] 3D RAM has to use these TSVs these [138:46] through silicon vas. And what this means [138:50] is that HBM as opposed to DDR5 memory as [138:54] an example uses about three times as [138:56] much more wafer capacity per gigabyte. [138:58] So more silicon required, three times [139:00] more and third party estimates put it at [139:03] above half of the cost of a B300 [139:07] physical package, which is insane. More [139:09] than 50% of the cost is just the HPM. [139:12] And the suppliers, the sell capacity [139:14] through contracts arrange approximately [139:16] 12 to 24 months ahead, which means that [139:18] for example, the 2026 supply has already [139:21] been sold out. And with the latest HPM4 [139:24] generation which introduces custom logic [139:27] based dyes, it kind of deepens the indep [139:30] inter independency between the product [139:33] and the memory. Um, which from multiple [139:36] spect perspectives may be good or bad in [139:38] the sense that this specific memory [139:40] depends on the processor the accelerator [139:42] that's being built for. um which causes [139:44] like this dual dependence and as long as [139:47] the two companies Nvidia and its memory [139:49] suppliers are in a good relationship [139:51] then there shouldn't be problems. Okay. [139:54] So when it comes to market dominance we [139:56] have Samsung leading DRAM and SKH highex [139:59] leading HBM. Here are the numbers from [140:02] uh quarter 1 2026 and estimates for HBM. [140:07] So, we have Samsung SK Hinx Micron and [140:10] then SKX Micron Samsung in the two [140:13] respective lists. And one of the [140:15] craziest stats from this video is the [140:18] DRAM industry revenue, which has [140:20] increased 144% from 2025 to 2026 up to [140:25] now. 165.7 billion to $44.3 billion. [140:29] Absolutely insane. Um, of course, one of [140:32] these reasons once again being that the [140:33] demand for HBM, which requires three [140:35] times more capacity, um, just means that [140:38] these companies are selling more HBM, [140:41] which itself requires more silicon, [140:44] which then exacerbates shortages, making [140:46] the demand even greater due to the [140:49] reduced supply. Okay, so we discussed [140:51] HBM being one of today's bottlenecks. [140:54] But if you look at a recent history [140:56] lesson, by 2023, [140:59] SEW was or co-ass chip on wafer on [141:02] substrate was one of the biggest factors [141:05] limiting accelerate output. So what's [141:08] going on here? Well, GPU dies and HPM [141:10] stacks need a package that connects them [141:12] at high bandwidth. And this is called [141:15] chip on wafer on substrate. And this [141:17] shortage was approximately from 2023 to [141:20] 2035. Even the chairman of TSMC made [141:24] that statement. And what seems like a [141:28] trivial component in the process of com [141:30] making a chip essentially a stage where [141:32] you take the two most expensive and [141:34] sophisticated components and put them on [141:36] an interposer in order to have them [141:39] communicate with each other was actually [141:41] the the bottleneck here. And this is in [141:43] part because there was new co-as [141:45] technologies being rolled out in this [141:48] time frame which it turns out needed [141:51] some time in order to reach high volume [141:53] manufacturing. And you can see that by [141:56] today the constraints on cos have [142:00] essentially gone the analysts have put [142:02] coass capacity up to 10x from 2023 [142:04] levels. And you can see that overall in [142:07] the supply chain here many times when [142:09] you have a intense shortage there's such [142:12] an intense need and push to increase [142:16] production for that specific component [142:18] that there actually sometimes is a glut [142:21] of that specific resource in the in the [142:24] succeeding years which may have like the [142:26] opposite effect of the shortage in terms [142:28] of causing there to be a decrease in [142:31] prices or demand. So let's talk about [142:34] what the packaging actually looks like [142:36] for a GB300. So first you have an [142:39] organic substrate which forms the base [142:41] of the accelerator package and this [142:43] carries power and signals to the circuit [142:44] while supporting the compute dies memory [142:46] stacks and wiring layer above it. And [142:48] then on top of this you have the cos L [142:51] which places an interposer with embedded [142:54] local silicon interconnects on the [142:56] organic substrate. What does this local [142:58] silicon do? It provides dense links [143:00] where dyes meet while the wiring plane [143:04] here behind the local silicon bridges [143:07] carries signal and powers across the [143:09] package. [143:11] Then we have the GPUs. Of course, these [143:14] HBM stacks are not actually laid out. [143:17] So, um, if you remember, they're [143:19] actually placed four vertically on top [143:21] of each other, but the diagram here just [143:23] doesn't fit. So you have these two GP [143:25] dies and eight 12 high HPM 3 E stacks [143:28] shared on the uh one interposer. And one [143:32] thing I didn't mention also is that even [143:34] though these two GPUs essentially [143:36] approach the reticle limit of the ASML [143:39] photo uh patterning system. This also [143:42] has a good thing for yield, which is to [143:44] say that if your GPU were to be a single [143:49] reticle limit and the size of both of [143:52] them combined, well then if we look at [143:54] back at the formula for the yields, then [143:56] you'll have much lower yield because a [143:59] single defect on one entire piece of the [144:03] GPU would mean the entire thing is gone. [144:05] Whereas now one defect means that only [144:07] one of the dies is ruined and the other [144:10] one can still be used. And then here the [144:12] wiring plane which is once again behind [144:15] or on underneath the GPUs is what [144:18] actually links the dyes to the nearby [144:20] HPM without any conventional memory [144:25] module bottlenecks that would be used if [144:27] you don't have this type of advanced [144:29] packaging. If we look at this from a [144:31] cross-section, we have a thermal lid [144:35] which closes over the assembled logic [144:36] and memory dies which protects the [144:38] package and transfers heat into the [144:39] cooling system on top. So right here the [144:43] result is one accelerator assembled from [144:45] separate components rather than one [144:47] monolithic chip. That's one [144:48] misconception. It's not just a single [144:51] constituent piece that's made in the [144:52] factory. It's many that are assembled [144:54] together in the advanced packaging [144:56] stage. And now we've arrived at the [144:59] seventh choke point that we will coin [145:01] for this video. In fact, TSMC is so [145:05] important to this industry that it is [145:07] twice a bottleneck. So we already talked [145:10] about the fact that it has leading edge [145:11] logic which is required for the GPU [145:13] design tape out. But not only that, but [145:15] for the advanced packaging which TSMC [145:17] also does to co-ass uh doing the logic [145:20] and HPM integration, this is also an [145:22] incredibly important part of the process [145:26] for creating these semiconductors [145:28] because with logic HPM interconnected [145:30] substrate assembly and test joined the [145:32] package is ready to enter rack [145:33] integration whereas without it you just [145:35] have a bunch of pieces that can't do [145:36] much without each other. So once these [145:38] chips are packaged then you want to [145:40] connect them and as we mentioned right [145:42] we have the scale up domain for GPUs [145:45] which in the case of the current [145:46] generation Nvidia GPUs uses NV link [145:50] through NV switch. So NVL link is the [145:52] actual port that is on the GPU itself [145:54] and then NV switch is a switch which [145:57] every single NV link is connected to [145:59] that allows the alltoall communication. [146:02] For example, on a NVL 72 rack, there are [146:06] 18 NV switches and 72 GPUs, which means [146:11] that every single GPU is connected to [146:12] each of the 18 switches. And each of the [146:15] 18 switches is conversely connected to [146:17] each GPU. And what this means is that [146:20] you can essentially send data across [146:23] many different streams and chunk it so [146:27] that you have essentially many different [146:29] chunks of data across many different uh [146:32] any many different switches on the [146:34] switch fabric in order to increase [146:35] bandwidth. [146:37] Then if we look at the scaleup domain, [146:39] this is between racks where you'll [146:41] likely have to go through the super [146:43] nick, the super network interface card [146:45] and then through some network spine. And [146:48] this is how you communicate between the [146:50] GPUs. And if we talk about transfer [146:52] rates, right, NVL link with these nine [146:55] NV switch trays facilitates 1.8 [146:58] terabytes per second birectional per GPU [147:01] and um in aggregate actually 130 [147:04] terabytes per second if you sum across [147:06] whereas the scale out is probably a few [147:09] order of magnitudes slower. It depends [147:11] on the specific system. Okay. So in part [147:14] six now we're going to talk about choke [147:16] points with respect to policy. So it's [147:18] less going to be technological and more [147:20] political. So I hope you guys are ready. [147:25] Let's talk about concentration. So [147:28] concentration makes policy coercive. And [147:30] what does this mean? It means that [147:31] governments can use the semiconductor [147:33] supply chain as leverage because [147:34] critical technologies and production sit [147:36] in a few countries and a few companies. [147:38] This results in export licenses, [147:41] investment rules and industrial [147:42] subsidies which shape which firms can [147:45] buy design uh buy and design tools, [147:47] equipment memory and advanced logic. I [147:49] was speaking with an Nvidia engineer [147:51] yesterday and he told me that a large [147:54] extent of to what extent Nvidia and [147:56] other uh semiconductor companies will [147:58] make or break profit is whether the US [148:02] policy towards China is positive or [148:03] negative in terms of export control and [148:05] to what extent for example they'll allow [148:07] them to sell certain GPUs. So it really [148:10] is important to consider the political [148:12] consequences of this extremely critical [148:17] and elusive technology. And if we look [148:20] at the prevailing export control which [148:23] has been between China and the US and [148:25] mainly China sorry the US applying [148:28] export control to China between 2019 and [148:30] 2024. These have widened from one [148:32] company to an entire technology stack [148:34] essentially. So in May 2019, for [148:36] example, Huawei was named um as [148:39] essentially an an entity which would be [148:42] restricted certain exports and then one [148:44] year later there was a foreign uh FDPR [148:48] which essentially means that certain [148:50] companies could not sell their equipment [148:52] to China. Then in 2022, Advanced [148:55] Technologies chips and fab tools were [148:58] regulated for export to China. And then [149:01] now in 2024 we have HBM first of all and [149:05] then 140 entities and 27 categories that [149:08] are all restricted export to China. And [149:10] you can see that from 20194 we have a [149:14] single firm to the capability required [149:16] to build advanced chips that has been [149:17] restricted. And you can see that this [149:20] demonstrates the extent to which the [149:23] political consequences of this are [149:25] increasing and the stakes are becoming [149:27] larger and larger. [149:29] Now, if we look at the story of Nvidia [149:32] access to the China market between [149:34] October 2023 and January 26, the policy, [149:38] as you can see, has repeatedly opened [149:40] and closed. This may or may not [149:42] essentially demonstrate the volatility [149:44] of the Trump administration policy, but [149:47] um from the H20 being designed and open [149:50] to licenses, parts reopen, production [149:52] halted, and on a case-by case basis, [149:54] there has been many different iterations [149:56] of this policy. And furthermore, even [149:59] now, China, it seems, is saying to [150:02] Chinese manufacturers and other [150:04] hyperscalers or data center companies in [150:07] China not to buy the chips. So, it may [150:09] have all been worth not that much for [150:11] Nvidia to go in this uh venture, but [150:14] only time will tell if the market will [150:16] open again for selling chips to China. [150:19] Now, if you look at outside of the AI [150:22] industry, these disputes can also spill [150:24] into the automotive industry. So in [150:26] September 2025, the Dutch government was [150:28] concerned over a company which had both [150:30] a Dutch and a Chinese presence and took [150:33] some action in order to prevent [150:36] technology transfer concerns. And then [150:38] what happened was that China blocked [150:40] exports of the same company that the [150:43] Dutch were trying to control. And these [150:47] exports that were blocked were from a [150:50] plant in Donguan which made automotive [150:52] semiconductor components. These are more [150:55] than 55 50 billion simple chips a year, [150:57] but it's all just mature nodes uh that [151:00] cost very little but are important for [151:01] making these expensive cars and sense [151:04] price mature nodes became part of the [151:06] bottleneck. Automakers though did warn [151:08] of production stoppages within days [151:11] because the plant once again chips more [151:12] than 50 billion simple chips a year and [151:15] it seems that the situation now has been [151:16] alleviated. But um you can expect more [151:19] and more likely of these similar [151:21] situations occurring in the future where [151:24] the simple export control law that might [151:28] be intro introduced to reduce AI [151:30] influence might also spill into [151:32] secondary industries. So now looking at [151:35] the Chinese AI strategy, one thing [151:36] that's interesting is that they trailed [151:38] they trade yield and power for [151:40] capability. So, Smick uses [151:43] multi-atterning, which we've already [151:44] discussed on deep ultraviolet exposures, [151:47] which gives an estimated yield of 20 to [151:49] 40%. which means that the estimated [151:52] price to you to to produce is 40 to 50 [151:54] 50% greater. But nevertheless, they're [151:57] still able to make their own racks with [151:59] Huawei that have four times the power of [152:03] one NVL72 [152:05] um and are greater than the aggregate [152:08] compute of a GB200 because it has uh [152:11] many more chips. So 384 and 16 racks. Of [152:14] course, it's not an apples to apples [152:15] comparison, but you can see that when [152:17] they're willing to trade yield and power [152:19] for capability, they will. And for [152:21] China, they don't really need to be [152:24] concerned about margins at the end of [152:26] the day because the government will [152:27] likely sponsor it. So, you can see a [152:29] much different approach here that is [152:30] really not market guided, but still [152:33] produces a legitimate uh AI accelerator. [152:38] Let's now talk about the domestic [152:40] Chinese supply chain and the [152:42] technological gaps. So if you look at [152:44] EUV, there's reports that they have a [152:47] prototype for a EV tool at 100 to 150 W. [152:53] And if we compare this, this is actually [152:56] below the ASML 2017 benchmark. So quite [152:59] far behind. And then if we talk about [153:01] DUV, it's a similar gap with respect to [153:03] HPM. They target HBM3 by end of 2026. Um [153:07] but according to analysts it's still [153:09] three to four years behind Korea. And [153:12] then EDA electronic design autom [153:15] automation does have a company called [153:18] Emperion which has 10 to 12% of the [153:20] Chinese market but advanced flows still [153:23] require foreign tools. So that would be [153:25] Cadence Synopsis and Seaman's EVA. And I [153:27] think we already discussed the monopoly [153:30] but if we actually go to the sub 10 [153:33] nanometer capacity instead of the sub [153:35] seven nanometer capacity we see to what [153:38] extent this is even greater. So 92% of [153:42] the share in 2022 below 10 nanometers [153:46] was owned by uh TSMC and capacity [153:50] concentration committed demand are [153:52] different measures of the same exposure [153:54] but this also shows that for the TSMC N2 [153:58] capacity we have commitments all the way [154:00] to Q2 2020 2027 for volume production [154:03] which means that there's going to be no [154:05] time soon when TSMC fab factories will [154:08] be sitting idle unless Unless of course [154:10] a Taiwan conflict occurred and this [154:12] would erase 9.6 billion 9.6% of global [154:16] GDP in one year and and result in 10.6 [154:20] trillion in models first year loss which [154:22] would be worse than COVID and um [154:26] essentially all previous financial [154:28] crisises. So God forbid this from [154:30] happening. Of course if this were to [154:31] happen it would likely be due to a US [154:33] China conflict. And we can already see [154:35] that the two AI stacks are diverging [154:37] although not yet dependent independent. [154:39] So in terms of accelerator you can [154:41] broadly classify the US into GPUs from [154:43] Nvidia and China into the Huawei Asend. [154:47] Then you have uh CUDA as the main [154:49] software for programming Nvidia GPUs and [154:52] then CNN which is what is used as kind [154:55] of the CUDA equivalent for Huawei. Then [154:57] when it comes to Foundaries the two [154:59] largest ones in the west and the east [155:00] are TSMC and SMIC. And then for tooling, [155:03] everything is pretty much domestic in [155:05] China um or is trying to be made [155:07] domestic. Of course, there's still [155:08] foreign dependencies, whereas in the US, [155:11] you have ASML plus the US/Japan [155:14] equipment. And with that being said, we [155:16] arrive from chip to system with a rack [155:20] that, like we said in the beginning of [155:21] the video, can draw 135 kW if we're [155:24] looking at the NVL 72 GB300 Ultra system [155:28] in particular. And this causes a [155:32] constraint on infrastructure for power [155:34] which we might see as a important theme [155:35] moving forward. In fact, power and [155:37] infrastructure is a video that I'm [155:39] considering on making a course next. And [155:41] if you're interested in that, then [155:42] definitely leave me a comment and tell [155:43] me what specifically you want to see [155:45] from such a video. But otherwise, the [155:48] accelerator reaches a data center now [155:50] that it's been put in the package. And [155:52] we've gone through and reported the [155:55] different parts of the semiconductor [155:57] supply chain that are critical. And all [156:00] of this leads into a $800 billion per [156:04] year capex. Let's quickly just go over [156:07] the different uh choke points since they [156:09] may or may not have been mentioned [156:10] specifically throughout the video. We [156:12] have the EDA synopsis and cadis as one [156:15] of the supply point choke points because [156:17] their software is indispensable. Then we [156:19] have the materials themselves which are [156:21] needed daily and without them there can [156:23] be massive shortages and stockpiling. We [156:26] saw that the neon prices that went up 4x [156:28] was due to Ukraine being invaded by [156:31] Russia. So that's number two. ASML [156:34] lithography enough said. And then TSMC [156:37] both for foundry and as advanced [156:40] packaging. And then Zeiss because ASML [156:44] depends on it for their mirrors. And [156:46] then finally, HBM because these three [156:48] manufacturers hold 90% of the global HPM [156:52] share. And if any of them were to go [156:56] under or have something happen to them, [156:58] that would be a massive shortening and [157:00] strain on HPM production, which would [157:03] lead to even more insane prices. So [157:06] that's all for this course on chips from [157:10] SAND to data center. I truly hope you [157:12] enjoyed and that you learned a lot. I [157:14] apologize if there's any mistakes. My [157:16] intent is to teach as much as possible [157:18] and to learn through teaching. So, if [157:20] you have any feedback, please let me [157:21] know. And if you made it this far, [157:23] thanks again. Have a great day.